Programmer’s Model

• To use a Cortex-M4 device with C language,

you only need to know the
– memory map,
– the peripheral programming information,
– the exception handling mechanism,
– and part of the programmer’s model.
 Programmer’s Model
• Processor mode and privilege levels for
software execution
• The processor modes are:
– Thread mode: Used to execute application
software. The processor enters Thread mode
when it comes out of reset. The CONTROL register
controls whether software execution is privileged
or unprivileged.
 Programmer’s Model
• Processor mode and privilege levels for
software execution
• The processor modes are:
– Handler mode: Used to handle exceptions. The
processor returns to Thread mode when it has
finished exception processing. Software execution
is always privileged.
 Registers and Special Registers
• To perform data processing and controls, a number
of registers are required inside the processor core.
• If data from memory are to be processed, they
have to be loaded from the memory to a register in
the register bank, processed inside the processor,
and then written back to the memory if needed.
• This is commonly called a “load-store architecture.”
 Registers and Special Registers
• The Cortex-M4 processor provides a register
bank of 13 general-purpose 32-bit registers
(R0-R12) and a number of special registers.
• The register bank contains sixteen 32-bit
registers.
– Most of them are general-purpose registers,
– but some have special uses.
 R0-R12
• Registers R0 to R12 are for general uses.
• Many of the Thumb instructions can only
access R0 to R7, which are also called the low
registers.
• Some instructions, like MOV (move), can be
used on all registers.
• The initial values of R0 to R12 at reset are
undefined.
 R13, Stack Pointer (SP)
• R13 is the stack pointer. It is used for accessing
the stack memory via PUSH and POP operations.
• There are physically two different stack pointers
in Cortex-M4.
• The main stack pointer (MSP) is the default stack
pointer after reset, and it is used when running
exception handlers.
• The process stack pointer (PSP) can only be used
in Thread mode (when not handling exceptions).
 R13, Stack Pointer (SP)
• It is not necessary to use the PSP.
• In many applications, the system can
completely rely on the MSP.
• The PSP is normally used in designs with an
OS.
 R14, Link Register (LR)
• R14 is the Link Register. The Link Register is
used for storing the return address of a
subroutine or function call.
• At the end of the subroutine or function, the
return address stored in LR is loaded into the
program counter so that the execution of the
calling program can be resumed.
 R15, Program Counter (PC)
• R15 is the Program Counter. It is readable and
writeable.
• A read returns the current instruction address
plus four (this is caused by the pipeline nature
of the design).
• Writing to R15 will cause a branch to take
place (but unlike a function call, the Link
Register does not get updated).
xPSR, combined Program Status Register

• The combined Program Status Register

provides information about program
execution and the ALU flags.
• It is consists of the following three Program
Status Registers (PSRs):
– Application PSR (APSR)
– Interrupt PSR (IPSR)
– Execution PSR (EPSR)
 Program Status Registers (PSRs)
• The APSR contains the current state of the condition flags from
previous instruction executions. The APSR contains the ALU flags:
– N (negative flag), Z (zero flag), C (carry or borrow flag), and V (overflow
flag).
– The common use of these flags is to control conditional branches.
• The IPSR contains the current executing interrupt service routine
(ISR) number.
• The EPSR contains the Thumb state bit, and the execution state
bits for either the:
– If-Then (IT) instruction
– Interruptible-Continuable Instruction (ICI) field for an interrupted load
multiple or store multiple instruction.
PRIMASK: Interrupt Mask Special Register

• The PRIMASK register is a 1-bit-wide interrupt

mask register.
• The PRIMASK register prevents activation of
all exceptions with configurable priority.
 Fault mask register
• The FAULTMASK register prevents activation of
all exceptions except for Non-Maskable
Interrupt (NMI).
 Base priority mask register
• The BASEPRI register defines the minimum
priority for exception processing. When
BASEPRI is set to a nonzero value, it prevents
the activation of all exceptions with same or
lower priority level as the BASEPRI value.
 CONTROL: Special Register
• As mentioned earlier, there are two stack
pointers in the Cortex-M4 processor.
• The stack pointer selection is determined by
the processor mode as well as the
configuration of the CONTROL register.
 Memory System Overview
• The Cortex-M4 processor has 4 GB of memory
address space.
 Stack Memory Operations
• Stack memory is a memory usage mechanism that
allows the system memory to be used as temporary
data storage that behaves as a first-in, last-out
buffer.
• One of the essential elements of stack memory
operation is a register called the stack pointer.
• The stack pointer is adjusted automatically each
time a stack operation is carried out.
• In the Cortex-M4 processor, the stack pointer is
register R13 in the register bank.
 Exceptions and Interrupts
• Exceptions are events that cause change to
program control.
• Instead of continuing program execution, the
processor suspends the current executing task
and executes a part of the program code
called the exception handler.
• After the exception handler is completed, it
will then resume the normal program
execution.
 Exceptions and Interrupts
• There are various types of exceptions, and
interrupts are a subset of exceptions.
• The Cortex-M4 processor supports up to 240
external interrupts (commonly referred as
IRQs) and an additional special interrupt called
the nonmaskable interrupt (NMI).
• The exception handlers for interrupt events
are commonly known as interrupt service
routines (ISRs).
 Exceptions and Interrupts
• Interrupts are usually generated by on-chip
peripherals, or by external input through I/O
ports.
• The number of available interrupts on the
Cortex-M4 processor depends on the
microcontroller product you use.
• In systems with more peripherals, it is possible
for multiple interrupt sources to share one
interrupt connection.
 Exceptions and Interrupts
• Besides the NMI and IRQ, there are a number
of system exceptions in the Cortex-M4
processor, primarily for OS use and fault
handling.
• Each exception has an exception number. This
number is reflected in various registers
including the IPSR and is used to define the
exception vector addresses.
Exceptions and Interrupts
 Nested Vectored Interrupt Controller
(NVIC)
• To prioritize the interrupt requests and handle
other exceptions, the Cortex-M4 processor has a
built-in interrupt controller called the Nested
Vectored Interrupt Controller (NVIC).
• The interrupt management function is controlled
by a number of programmable registers in the
NVIC.
• These registers are memory mapped, with the
addresses located within the System Control Space
(SCS).
 Nested Vectored Interrupt Controller
(NVIC)
• The NVIC supports a number of features:
– Flexible interrupt management
– Nested interrupt support
– Vectored exception entry
– Interrupt masking
 Flexible Interrupt Management
• In the Cortex-M4 processor, each external interrupt
can be enabled or disabled and can have its pending
status set or clear by software.
• It can also accept exception requests at signal level
(interrupt request from a peripheral remain asserted
until the interrupt service routine clears the
interrupt request), as well as an exception request
pulse (minimum 1 clock cycle).
• This allows the interrupt controller to be used with
any interrupt source.
 Nested Interrupt Support
• In the Cortex-M4 processor, each exception has a priority
level.
• The priority level can be fixed or programmable.
• When an exception occurs, such as an external interrupt,
the NVIC will compare the priority of this exception to the
current level.
• If the new exception has a higher priority,
– the current running task will be suspended.
– Some of the registers will be stored on to the stack memory, and
– the processor will start executing the exception handler of the
new exception.
 Interrupt Masking
• The NVIC in the Cortex-M4 processor provides
an interrupt masking feature via the PRIMASK,
FAULTMASK and BASEPRI special registers.
• This can disable all exceptions except hard
fault and NMI.
• This masking is useful for operations that
should not be interrupted such as time critical
control tasks or real-time multimedia codecs.
 System Control Block (SCB)
• The System Control Space (SCS) also contains a
number of other registers for system
management. This is called the System Control
Block (SCB).
• It contains registers for sleep mode features and
system exception configurations, as well as a
register containing the processor identification
code (which can be used by in circuit debuggers
for detection of the processor type).
 Fault handling
• Faults are a subset of the exceptions. The following
generate a fault:
– A bus error on:
• An instruction fetch or vector table load
• A data access
– An internally-detected error such as an undefined
instruction
– Attempting to execute an instruction from a memory
region marked as Non-Executable (XN).
– A privilege violation or an attempt to access an
unmanaged region causing an MPU fault.
 Power management
• The STM32 and Cortex-M4 processor sleep
modes reduce power consumption:
– Sleep mode stops the processor clock. All other
system and peripheral clocks may still be running.
– Deep sleep mode stops most of the STM32 system
and peripheral clocks. At product level, this
corresponds to either the Stop or the Standby
mode.
 Entering sleep mode
• Wait for interrupt The wait for interrupt instruction, WFI,
causes immediate entry to sleep mode (unless the wake-
up condition is true,
• Wait for event The wait for event instruction, WFE,
causes entry to sleep mode depending on the value of a
one-bit event register. When the processor executes a
WFE instruction, it checks the value of the event register:
– 0: the processor stops executing instructions and enters sleep
mode
– 1: the processor clears the register to 0 and continues
executing instructions without entering sleep mode.
 Entering sleep mode
• Sleep-on-exit If the SLEEPONEXIT bit of the
SCR is set to 1, when the processor completes
the execution of an exception handler it
returns to Thread mode and immediately
enters sleep mode. Use this mechanism in
applications that only require the processor to
run when an exception occurs.
 Wakeup from sleep mode
• Wakeup from WFI or sleep-on-exit Normally,
the processor wakes up only when it detects
an exception with sufficient priority to cause
exception entry.
• Wakeup from WFE The processor wakes up if:
– it detects an exception with sufficient priority to
cause exception entry
– it detects an external event signal.
 CMSIS - Cortex Microcontroller Software
Interface Standard
• The ARM® Cortex® Microcontroller Software Interface Standard
(CMSIS) is a vendor-independent hardware abstraction layer for
the Cortex-M processor series and specifies debugger interfaces.
• Standardizing the software interfaces across all Cortex-M silicon
vendor products, especially when creating new projects or
migrating existing software to a new device, means significant cost
reductions.
• The CMSIS enables consistent and simple software interfaces to
the processor for interface peripherals, real-time operating
systems, and middleware.
• It simplifies software re-use, reducing the learning curve for new
microcontroller developers and cutting the time-to-market for
devices.
CMSIS