Unit 3 10 Error
Unit 3 10 Error
Unit 3 10 Error
and Correction
CS44 Data Communications
2
Physical Layer - Revisited
• Physical layer concerned with the following
Representation of bits(encoding and modulating
– digital-digital; analog-digital; digital-analog;
analog-analog)
3
Data Link Layer
• Transmitted from one node to the next can become corrupted in passage
• Require a mechanism for detecting and correcting errors
4
Error Control
• At the data-link layer, corrupted frame needs to be corrected before it
continues its journey to other nodes
• Detecting errors
◦ block coding
◦ cyclic codes – CRC
◦ checksums
• Correcting errors
◦ Forward error correction
◦ Hamming distance
◦ XORing of packets
◦ interleaving chunks
◦ compounding high and low resolutions packets
◦ Automatic repeat request (ARQ)
• Most link-layer protocols simply discard the frame and let the upper-layer
protocols handle the retransmission of the frame
5
Error Detection and Correction
Issues
• Types of Errors
◦ Single-bit and burst error
• Redundancy
◦ some extra bits with our data
• Detection versus Correction
• Coding
◦ block coding and convolution coding
6
Types of Errors
• Single-bit errors: only 1 bit of a given data unit is changed
from 1 to 0 or from 0 to 1
8
Coding
• Process of adding redundancy for error detection or
correction creates a relationship between the redundant
bits and the actual data bits
• Two types:
◦ Block codes
◦ Divides the data to be sent into a set of blocks
◦ Extra information attached to each block
◦ Memoryless
◦ Convolutional codes
◦ Treats data as a series of bits, and computes a code over a continuous series
◦ The code computed for a set of bits depends on the current and previous input
9
Detection versus Correction
• correction of errors is more difficult than the detection
• error detection only looking to see if any error has
occurred not the number of corrupted bits
◦ No difference between a single-bit error and a burst error
• error correction need to know the exact number of bits
that are corrupted with their location in the message
◦ 8-bit data unit
◦ to correct a single error need to consider eight possible error locations
◦ to correct two errors need to consider 28 (permutation of 8 by 2) possible error
locations
◦ Receiver find difficulty to correct 10 errors in a data unit of 1000 bits
10
Notes
• An error-detecting/correcting code can detect/correct only
the types of errors for which it is designed
◦ Other types of errors may remain undetected.
• There is no way to detect/correct every possible error!
11
XOR Operation
• Main operation for computing error detection/correction
codes
◦ Simpler and faster than addition; no carry bit!
• Similar to modulo-2 addition
12
Block Coding
• Message is divided into k-bit blocks
◦ Known as datawords
• r redundant bits are added
◦ Blocks become n=k+r bits
◦ Known as codewords • 2n − 2k codewords that are not used
• invalid or illegal
• If the receiver receives an invalid
codeword, this indicates that the
data was corrupted during
transmission.
13
Example: 4B/5B Block Coding
Data Code Data Code
0000 11110 1000 10010
14
How can errors be detected by using
block coding?
• Two conditions the receiver follows to detect a change in
the original codeword
1. The receiver has (or can find) a list of valid codewords
2. The original codeword has changed to an invalid one
15
Error Detection in Block Coding
17
Hamming Distance
Hamming Distance between two words is
the number of differences between
corresponding bits.
• Hamming distance between the received codeword and the sent
codeword is the number of bits that are corrupted during
transmission important for error detection
• if the Hamming distance between the sent and the received
codeword is not zero, the codeword has been corrupted during
transmission
◦ Found by XOR operation (⊕) on the two words and count the number of 1s
in the result
• d(000, 011) is 2 because (000 ⊕ 011) is 011 (two 1s)
• d(10101, 11110) is 3 because (10101 ⊕ 11110) is 01011 (three 1s)
18
Minimum Hamming Distance
The minimum Hamming distance
is the smallest Hamming distance
between
all possible pairs in a set of
• Find the minimum Hamming Distance of the following
codebook codewords.
0000
minimum Hamming Distance = 3 0
0101
1
1010
1 19
Detection Capability of Code
• To guarantee the detection of up to s-bit errors, the
minimum Hamming distance in a block code must be
dmin
min
=s+1
• If the codeword 101 is sent and one error occurs, the received codeword
does not match any valid codeword
• If two errors occur, however, the received codeword may match a valid
codeword and the errors are not detected
21
Linear Block Codes
• Two types
◦ linear block codes – today's choice
◦ requires the knowledge of abstract algebra (particularly Galois fields)
◦ a code in which the exclusive OR (addition modulo-2) of two valid codewords creates another valid
codeword
◦ nonlinear block codes - not as widespread because their structure makes
theoretical analysis and implementation difficult
22
Minimum Distance for Linear Block
Codes
• the number of 1s in the nonzero valid codeword with the
smallest number of 1s
• So the minimum Hamming distance is dmin = 2.
23
Common Detection Methods
• Parity check
• Cyclic Redundancy Check
• Checksum
24
Parity Check
• Most common linear block code, least complex
• Single bit (called the parity bit) is added to a block
◦ a k-bit dataword is changed to an n-bit codeword where n = k + 1
• Two schemes:
◦ Even parity – Maintain even number of 1s
◦ Extra bit used to make the total number of 1s in the codeword even
◦ E.g., 1011 10111
◦ Odd parity – Maintain odd number of 1s
◦ Extra bit used to make the total number of 1s in the codeword odd
◦ E.g., 1011 10110
26
Example: Parity Check
Suppose the sender wants to send the word world. In
ASCII the five characters are coded (with even parity) as
1110111 1101111 1110010 1101100
1100100
The following shows the actual bits sent
11101110 11011110 11100100 11011000
Receiver receives this sequence of words:
11001001
11111110 11011110 11101100 11011000 11001001
Which blocks are accepted? Which are rejected?
11111110 11011110 11101100 11011000 11001001
R A R
A A
27
Parity-Check: Encoding/Decoding
r0 = a3 + a2 +a1 +a0
(modulo-2) s0 = b3 + b2 +b1 +b0+q0
(modulo-2)
Rule to make total number of 1s in the codeword is even: Rule of the decision logic analyzer : If s0=0, no
If the number of 1s is even, r0=0 else r0=1 detectable error in the received codeword (accept)
else detectable error (discard)
28
Parity-Check: transmission
scenarios
• Assume the sender dataword 1011 with codeword is 10111, which is
sent to the receiver.
Receiver Scenario received syndrome data Note
codeword word
No error occurs 10111 0 1011 -
One single-bit error 10011 1 Not -
- changes a1 created
One single-bit error 10110 1 Not none of the dataword bits are corrupted still no dataword
changes r0 created is created because the code is not sophisticated enough to
show the position of the corrupted bit.
error changes r0 and 00110 0 0011 dataword is wrongly created due to the syndrome value.
a second error The simple parity-check decoder cannot detect an even
changes a3 number of errors. The errors cancel each other out and
give the syndrome a value of 0.
3-bits—a3, a2, and 01011 1 Not shows that the simple parity check, guaranteed to detect
changed by errors created one single error, can also find any odd number of errors.
29
Cyclic Codes
• Special linear block codes
• In a cyclic code, rotating a codeword always results in another codeword
◦ n the rightmost equation, the last bit of the first word is wrapped around and
becomes the first bit of the second word
• Example: Consider the bits in the first word a0 to a6, and the bits in the
second word b0 to b6, we can shift the bits by using the following
b1 = a0
b2 = a1
b3 = a2
b4 = a3 1011000 is a codeword cyclically left-shift
b5 = a4 Result is 0110001 also a codeword
b6 = a5
b0 = a6
30
Cyclic Redundancy Check
(CRC)
• A subset of cyclic codes
• Has both the linear and cyclic properties
• Used in networks such as LANs and WANs
• A CRC code with C(7, 4)
31
CRC Encoder/Decoder
If the syndrome bits are all 0s, the 4 leftmost bits of the
codeword are accepted as the dataword (interpreted as
One possible design: no error); otherwise, the 4 bits are discarded (error).
k bits (4 here)
Added n − k (3 here)
0s to the right-hand
side
(modulo-2 division)
divisor of size n − k + 1
(4 here), predefined
and agreed upon
remainder produced
by checker
Quotient is discarded;
remainder (r2r1r0) is
appended to dataword
to create codeword
copy of all n bits is fed
to the checker
n bits (7 here)
32
CRC Generator
Division in CRC encoder: • Modulo-2 binary division
• Addition and subtraction are the same use
XOR operation to do both
• Each step: a copy of the divisor is XORed
with the 4 bits of the dividend
• Result (remainder) is 3 bits (in this
case), which is used for the next step
after 1 extra bit is pulled down to make
it 4 bits long
• Note: If the leftmost bit of the dividend
(or the part used in each step) is 0, the
step cannot use the regular divisor; we
need to use an all-0s divisor
• When there are no bits left to pull
How the divisor 1011 is chosen? down, we have a result
• 3-bit remainder forms the check bits (r2, r1,
Depends on the expectation we have from the
code- we will discuss this in polynomials. and r0). They are appended to the dataword
to create the codeword
33
Checking CRC
Division in the CRC decoder for two cases: division process as the encoder
no error
a single error
Remainder of the division is the syndrome
34
Polynomial Representation
• More common representation than binary form in cyclic codes
• Easy to analyze
• Divisor is commonly called generator polynomial
• Binary pattern can be represented as a polynomial with
coefficients of 0 and 1
◦ The power of each term shows the position of the bit; the coefficient
shows the value of the bit.
35
Polynomial Operations
• Degree of a polynomial highest power in the polynomial
◦ 1 less than the number of bits in the pattern
◦ the degree of the polynomial x6 + x + 1 is 6
◦ The bit pattern in this case has 7 bits
38
Cyclic Code Encoder Using
Polynomials
• Creation of a codeword from a dataword
Binary Division in CRC encoder CRC division using polynomials
• Process is shorter
• Dataword 1001 is represented as x3 + 1
• Divisor 1011 is represented as x3 + x + 1
• Augmented dataword is x6 + x3 we have left-shifted
the dataword 3 bits (multiplying by x3)
• Continue to divide until the degree of the remainder
is less than the degree of the divisor
In a polynomial representation, the divisor is normally referred to as the generator polynomial
The divisor in a cyclic code is normally called the generator polynomial or simply the generator
39
Cyclic Code Analysis
• Find its capabilities by using polynomials
◦ Polynomial with binary coefficients: f(x)
◦ Dataword: d(x)
◦ Codeword: c(x)
◦ Generator: g(x)
◦ Syndrome: s(x)
◦ not zero one or more bits is corrupted
◦ Zero either no bit is corrupted or Some bits are corrupted but the decoder failed to
detect any errors
◦ Error: e(x)
40
Cyclic Code Analysis
• Find the criteria that must be imposed on the generator as
part of analysis
◦ g(x) detect the type of error we want to be detected
1. Received codeword is the sum of the sent codeword and the error
Received codeword = c(x) + e(x)
2. receiver divides the received codeword by g(x) to get the syndrome
41
Some Specific Errors
• Let us see how 4-specific errors can be caught by a well
designed g(x)
◦ Single-Bit Error
◦ Two Isolated Single-Bit Errors
◦ Odd Numbers of Errors
◦ Burst Errors
42
I. Single-Bit Error
• What should the structure of g(x) be to guarantee the
detection of a single-bit error?
◦ Single-bit error is e(x) = xi, where i is the position of the bit
◦ If a single-bit error is caught, then xi is not divisible by g(x) -mean
that there is a remainder
◦ If the generator has more than one term and the coefficient of x0 is
1, all single-bit errors can be caught.
43
I. Single-Bit Error …
• Which of the following g(x) values guarantees that a single-bit error is
caught? For each case, what is the error that cannot be caught?
a. x + 1 b. x3 c. 1
SN g(x) Single-bit error caught? error that cannot be caught
a. x+1 No xi can be divisible by x + 1 -
When receiver performs xi /(x+1), result has a
remainder (the syndrome is nonzero)
Any single-bit error can be caught
b. x3 If i is equal to or greater than 3, xi is divisible by If the corrupted bit is in position 4 or
g(x). above, the receiver is fooled into
When receiver performs xi/x3 , result/syndrome believing that there is no error,
is zero although there might be the one.
All single-bit errors in positions 1 to 3 are caught.
c. 1 All values of i make xi divisible by g(x). This g(x) is useless because it means the
No single-bit error can be caught codeword is just the dataword
augmented with n − k zeros
44
II. Two Isolated Single-Bit Errors
• Under what conditions can this type of error be caught?
◦ Representation for type of error is e(x) = xj+ xi.
distance between
the two errors
45
II. Two Isolated Single-Bit Errors
• We can write e(x) = xj+ xi = xi+(j-i)+ xi = xi x(j-i)+ xi = xi(xj–i + 1)
• If g(x) has more than one term and one term is x0,
◦ It can divide xj–i + 1 no error detected
◦ it cannot divide xi detect one error at position i
• To detect two isolated errors
◦ g(x) must not divide xt + 1, where t is between 0 and n − 1.
◦ t = 0 is meaningless and t = 1 is needed
◦ This means t should be between 2 and n – 1.
If a generator cannot divide xt + 1 (t between 0 and n - 1), then all isolated double
errors can be detected.
46
II. Two Isolated Single-Bit Errors
• Find the status of the following generators related to two
isolated, single-bit errors
• a. x + 1 b. x4 + 1 c. x7 + x6 + 1 d. x15 + x14 + 1
SN Generator Detect two isolated errors?
a. x+1 very poor choice for a generator. Any two errors next to each other
cannot be detected
b. x4 + 1 cannot detect two errors that are four positions apart
c. x7 + x 6 + 1 good choice
d. x15 + x14 + 1 cannot divide any error of type x t + 1 if t is less than 32,768.
A codeword with two isolated errors that are next to each other or
up to 32,768 bits apart can be detected by this generator
47
III. Odd Numbers of Errors
• A generator with a factor of x + 1 can catch all odd
numbers of errors
• This means that we need to make x + 1 a factor of any
generator
◦ Remember that if it is only x + 1, it cannot catch the two adjacent
isolated errors
• For example, x4 + x2 + x + 1 can catch all odd-numbered
errors since it can be written as a product of the two
polynomials x + 1 and x3 + x2 + 1
48
IV. Burst Errors
• A burst error is of the form e(x) = (x j + . . . + xi)
◦ A burst error - can have two terms or more
◦ Two isolated single-bit errors - can only have two terms
• We can factor out xi and write the error as xi (xj-i + . . . + 1)
• If our generator can detect a single error (minimum
condition for a generator), then it cannot divide x i
• What we should worry about are those generators that
divide (xj-i + . . . + 1)
• If xr + . . . + 1 is the generator polynomial, the remainder
of (xj-i + . . . + 1)/(xr + . . . + 1 ) must not be zero
49
IV. Burst Errors
• Consider the L is the length of the error, j − i = L − 1
• Case 1: All burst errors with L ≤ r will be detected
◦ If j − i < r, the remainder can never be zero
◦ replace j − i with L − 1, L − 1 < r or L < r + 1
• Case 2: All burst errors with L = r + 1 will be detected with probability 1 –
(1/2)r–1
◦ If j − i = r, or L = r + 1, the syndrome is 0 and the error is undetected
◦ Probability of undetected burst error of length r + 1 is (1/2)r–1
◦ For example, if our generator is x14 + x3 + 1, in which r = 14, a burst error of length L = 15
can slip by undetected with the probability of (1/2)14–1 or almost 1 in 10,000.
• ❑ All burst errors with L > r + 1 will be detected with probability 1 – (1/2)r
◦ If j − i > r, or L > r + 1, the syndrome is 0 and the error is undetected.
◦ Probability of undetected burst error of length greater than r + 1 is (1/2)r
◦ For example, if our generator is x14 + x3 + 1, in which r = 14, a burst error of length greater
than 15 can slip by undetected with the probability of (1/2)14 or almost 1 in 16,000 cases.
50
IV. Burst Errors
• Find the suitability of the following generators in relation to burst errors of
different lengths.
a. x 6 + 1 b. x 18 + x7 + x + 1 c. x32 + x23 + x7 + 1
SN generators
a. x6 + 1 Case 1: detect all burst errors with a length less than or equal to 6 bits
r=6 (L<=6)
Case 2: 3 out of 100 burst errors with length 7 (L=r+1 = 6+1) will slip by
(Detected =1 – (1/2)r–1 = 1 – (1/2)6–1 = 1-0.03125 = 0.96875 = 97%)
Case 3: 16 out of 1000 burst errors of length 8 or more will slip by
(Detected = 1 – (1/2)r = 1 – (1/2) 6 = 0.984375 = 984 in 1000 burst error)
b. x18 + x7 + x + 1 Case 1: all burst errors with a length less than or equal to 18 bits
r=18 Case 2: 8 out of 1 million burst errors with length 19 will slip by;.
Case 3: 4 out of 1 million burst errors of length 20 or more will slip by
c. x32 + x23 + x7 + Case 1: all burst errors with a length less than or equal to 32 bits
1 Case 2: 5 out of 10 million burst errors with length 33 will slip by;.
Case 3: 3 out of 10 million burst errors of length 34 or more will slip by
51
Criteria for Good Polynomial Generator
• A good polynomial generator needs to have the following
characteristics:
1. It should have at least two terms.
2. The coefficient of the term x 0 should be 1
3. It should not divide x t + 1, for t between 2 and n – 1
4. It should have the factor x + 1.
52
Standard CRC Polynomials
• Some standard polynomials used by popular protocols for
CRC generation along with the corresponding bit pattern
53
Advantages of Cyclic Codes
• A very good performance in detecting single-bit errors,
double errors, an odd number of errors, and burst errors.
• Easily implemented in hardware and software
• Fast when implemented in hardware
• This has made cyclic codes a good candidate for many
networks
• Other Cyclic Codes
◦ Simple cyclic codes (discussed till now) - the check bits and syndromes can be calculated
by simple algebra
◦ Reed- Solomon code - More powerful polynomials that are based on abstract algebra
involving Galois fields
◦ used today for both detection and correction
54
Cyclic Codes – Hardware Implementation
• encoder and decoder can easily and cheaply be
implemented in hardware by using a handful of electronic
devices
• Also, a hardware implementation increases the rate of
check bit and syndrome bit calculation
•Hardware implementation includes hardwired design of
◦ Divisor in CRC
◦ Augmented Dataword
◦ Remainder
◦ General Design
55
Divisor
• Make a fixed (hardwired) divisor knowing the divisor pattern
considering
1. The divisor is repeatedly XORed with part of the dividend
2. The divisor has n − k + 1 bits which either are predefined or are all 0s.
The choice was based on the leftmost bit of the part of the augmented
data bits (0000 or predefined divisor) that are active in the XOR
operation.
3. Only n − k bits of the divisor are needed in the XOR operation.
◦ The leftmost bit is not needed because the result of the operation is always 0, no matter what
the value of this bit
if the leftmost bit of the part of the
dividend to be used in this step is
1, the divisor bits (d2d1d0 ) are 011;
if the leftmost bit is 0, the divisor
bits are 000
56
Augmented Dataword
• The divisor bits are aligned with the appropriate part of
the augmented dataword
• shift the bits of the augmented dataword to the left
(opposite direction) to align the divisor bits with the
appropriate part
• There is no need to store the augmented dataword bits
57
Remainder
• n − k bits remainder use n − k registers (single-bit
storage devices) to hold these bits
• Modified division process to find the final remainder of the
division in hardware (or even in software)
1. We assume that the remainder is originally all 0s (000 in our
example)
2. At each time click (arrival of 1 bit from an augmented dataword),
repeat the following two actions:
1. Use the leftmost bit to make a decision about the divisor (011 or 000).
2. The other 2 bits of the remainder and the next bit from the augmented dataword
(total of 3 bits) are XORed with the 3-bit divisor to create the next remainder
58
Simulation of division in CRC
encoder
24-Registers
21-XOR devices
59
Practical Simulation of division in CRC
encoder
• Two modifications for simpler and less expensive design
◦ No need to keep the intermediate values of the remainder bits
◦ Need only the final bits need only 3 registers instead of 24
◦ After the XOR operations, we do not need the bit values of the
previous remainder
◦ two are enough instead of 21 XOR devices because the output of an XOR operation in
which one of the bits is 0 is simply the value of the other bit
◦ This other bit can be used as the output
• A 1-bit shift register holds a bit for a duration of one clock time
• At a time click, the shift register accepts the bit at its input port, stores the new bit, and
displays it on the output port
• The content and the output remain the same until the next input arrives
• Connecting several 1-bit shift registers together looks as if the contents of the register
are shifting (shift registers)
60
General Design of encoder and decoder of a CRC
code
63
Checksum - simple example
• Suppose the message is a list of five 4-bit numbers that we want
to send to a destination. In addition to sending these numbers,
we send the sum of the numbers.
• For example, if the set of numbers is (7, 11, 12, 0, 6), we send (7,
11, 12, 0, 6, 36), where 36 is the sum of the original numbers.
• The receiver adds the five numbers and compares the result
with the sum
• If the two are the same, the receiver assumes no error, accepts
the five numbers, and discards the sum
• Otherwise, there is an error somewhere and the message is not
accepted.
64
Checksum - example
• Drawback - Each number can be written as a 4-bit word
(each is less than 15) except for the sum
• One solution is to use one’s complement arithmetic
◦ In this arithmetic, we can represent unsigned numbers between 0
and 2m − 1 using only m bits
◦ If the number has more than m bits, the extra leftmost bits need to
be added to the m rightmost bits (wra
65
One’s complement arithmetic
• Complement of a number completing all bits (changing
all 1s to 0s and all 0s to 1s)
◦ same as subtracting the number from 2m − 1
• Two 0s: one positive and one negative, which are
complements of each other
◦ The positive zero has all m bits set to 0
◦ The negative zero has all bits set to 1 it is 2m − 1
• If we add a number with its complement, we get a negative
zero (a number with all bits set to 1)
66
Checksum - example
• The decimal number 36 in binary is 100100
• To change it to a 4-bit number - we add the extra leftmost
bit to the right four bits
10 0100
67
Checksum - example
• The receiver can add the first five numbers in one’s
complement arithmetic
• If the result is 6, the numbers are accepted; otherwise, they
are rejected 1111
+ 0110
10 0100 1111 10101
+0000
Number Binary
0111 0011 1111 0110
7 0111 +1011 +1100 Result
11 1011 10010 1111
12 1100
0 0000 0011
6 0110
68
Checksum - example
• How to make the receiver job easy?
• Send the complement of the sum checksum
• Eg. The sender adds all five numbers in one’s complement
to get the sum = 6
• The sender then complements the result to get the
checksum = 9, which is 15 − 6.
• The sender sends the five data numbers and the checksum
(7, 11, 12, 0, 6, 9)
69
Checksum - example
• If there is no corruption in transmission, the receiver
receives (7, 11, 12, 0, 6, 9) and adds them in one’s
complement to get 15
• When the receiver adds all five numbers (including the
checksum), if it gets a negative zero, the message is
accepted; otherwise, it is rejected
Result of first
five numbers
1111 0110
+ 0110 + 1001
10101 1111 negative zero complement
9
A dd
0110 Positive zero
70
Checksum - example
71
Internet Checksum
• has used a 16-bit checksum
• The sender or the receiver uses five steps
72
Algorithm to calculate Internet
checksum
all computers today do calculation
in two’s complement. Hence,
calculates the sum of
the data units in two’s
complement
73
Internet Checksum -
Performance
• uses a small number of bits (16) to detect errors in a
message of any size (sometimes thousands of bits)
• Problem: Not as strong as the CRC in error-checking
capability as it is not weighted
◦ It treats each data item equally where the order of data items is
immaterial to the calculation
◦ For example, if the value of one word is incremented and the value of another word is
decremented by the same amount, the two errors cannot be detected because the sum
and checksum remain the same.
◦ Also, if the values of several words are incremented but the sum and the checksum do
not change, the errors are not detected
• Solution:
◦ Fletcher and Adler have proposed some weighted checksums that
eliminate the first problem
74
Fletcher Checksum
• Devised to weight each data item according to its position
• Fletcher has proposed two algorithms:
◦ 8-bit Fletcher: calculates on 8-bit data items/octets and creates a
16-bit checksum
◦ modulo 256 (28) calculation
◦ uses two accumulators, L and R. The first (L) simply adds data items together; the
second (R) adds a weight to the calculation
◦ many variations of the 8-bit Fletcher algorithm
◦ 16-bit Fletcher: calculates on 16-bit data items and creates a 32-bit
checksum
◦ The modulo 65,536 calculation
75
Algorithm to calculate an 8-bit Fletcher
checksum
76
Adler Checksum
• 32-bit checksum
• It is similar to the 16-bit Fletcher with three differences
1. Calculation is done on single bytes instead of 2 bytes at a time
2. The modulus is a prime number (65,521) instead of 65,536
3. R is initialized to 1 instead of 0
• It has been proved that a prime modulo has a better
detecting capability in some combinations of data
77
Algorithm to calculate an Adler
checksum
78
Forward Error Correction (FEC)
• If error detected using the previous error detection techniques,
the message is discarded which requires retransmission
• Retransmission of corrupted and lost packets is not useful for
real-time multimedia transmission because it creates an
unacceptable delay in reproducing: we need to wait until the
lost or corrupted packet is resent
• Need to correct the error or reproduce the packet immediately
◦ referred to as FEC techniques
◦ Hamming Distance
◦ Using XOR
◦ Chunk Interleaving
◦ Combining Hamming Distance and Interleaving
◦ Compounding High- and Low-Resolution Packets
79
Error Correction in Block
Coding
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Using Hamming Distance
• To detect s-errors, the minimum Hamming distance should
be dmin = s + 1
• For error correction, we definitely need more distance
• It can be shown that to correct t errors, we need to have
dmin = 2t + 1
◦ a lot of redundant bits need to be sent with the data
• Consider the famous BCH code: if data is 99 bits, we need
to send 255 bits (extra 156 bits) to correct just 23 possible
bit errors
◦ Most of the time we cannot afford such a redundancy
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Correction Capability of Code
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Using XOR
• Use the property of the exclusive OR operation
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Chunk Interleaving
• FEC in multimedia to allow some small chunks to be missing at
the receiver
• Missing all the chunks belonging to the same packet not
afforded
◦ Can afford to let one chunk be missing in each packet
• Steps:
◦ Divide each packet into 5 chunks (normally the number is much larger)
◦ Create data chunk by chunk (horizontally), but combine the chunks into
packets vertically
◦ Each packet sent carries a chunk from several original packets
◦ If the packet is lost, only one chunk in each packet can be missed, which
is normally acceptable in multimedia communication
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Chunk Interleaving
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Combining Hamming Distance and
Interleaving
• Hamming distance and interleaving can be combined
◦ First create n-bit packets that can correct t-bit errors Hamming
distance
◦ Then interleave m rows and send the bits column by column
• Automatically correct burst errors up to m × t-bit errors
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Compounding High- and Low-Resolution
Packets
• Create a duplicate of each packet with a low-resolution redundancy
• Combine the redundant version with the next packet
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Compounding High- and Low-Resolution
Packets
• Created four low-resolution packets out of five high-
resolution packets and send with next high resolution
packet
• If a packet is lost, the low-resolution version from the next
packet is used if the lost packet is not the last one
• Note: the low-resolution section in the first packet is empty
• If the last packet is lost, it cannot be recovered
• The audio and video reproduction does not have the same
quality, but the lack of quality is not recognized most of the
time.
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Summary
• Data can be corrupted during transmission
• Some applications require that errors be detected and
corrected
• In a single-bit error, only one bit in the data unit has changed
• A burst error means that two or more bits in the data unit have
changed
• To detect or correct errors, we need to send extra (redundant)
bits with data
• There are two main methods of error correction: forward error
correction and correction by retransmission
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Summary …
• Coding schemes categories: block coding and convolution
coding
• In coding, modulo-2 arithmetic is used
• Operations in this arithmetic: addition and subtraction give
the same results using the XOR (exclusive OR) operation
• In block coding
◦ Divide the message into blocks, each of k bits, called datawords
◦ Add r redundant bits to each block to make the length n = k + r
◦ The resulting n-bit blocks are called codewords
◦ Errors be detected by using the following two conditions:
◦ The receiver has (or can find) a list of valid codewords.
◦ The original codeword has changed to an invalid one.
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Summary …
• The Hamming distance between two words is the number
of differences between corresponding bits
• The minimum Hamming distance is the smallest Hamming
distance between all possible pairs in a set of words
• To guarantee the detection of up to s errors in all cases, the
minimum Hamming distance in a block code must be dmin =
s+1
• To guarantee correction of up to t errors in all cases, the
minimum Hamming distance in a block code must be dmin =
2t + 1
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Summary …
• In a linear block code, the exclusive OR (XOR) of any two valid
codewords creates another valid codeword.
• A simple parity-check code is a single-bit error-detecting code
in which n = k + 1 with dmin = 2
• A simple parity-check code can detect an odd number of errors
• Cyclic codes are special linear block codes with one extra
property- if a codeword is cyclically shifted (rotated), the result
is another codeword
• A category of cyclic codes called the cyclic redundancy check
(CRC) is used in networks such as LANs and WANs.
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Summary …
• A pattern of 0s and 1s can be represented as a polynomial
with coefficients of 0 and 1
• Traditionally, the Internet has been using a 16-bit
checksum, which uses one’s complement arithmetic
• In this arithmetic, unsigned numbers between 0 and 2n −1
are represented using only n bits.
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