Digital Electronics (203105201)

Alpita makwana, Assistant Professor

Mechatronics Engineering
 CHAPTER-3

Combinational Digital Circuits

Binary Adders and Subtractors, Parallel binary adder & Subtractor, serial adder, BCD
adder, carry look-ahead adder, Multiplexer, De-Multiplexer/Decoders, popular MSI
chips, Magnitude comparator, parity checker/generator, code converters, priority
encoders, decoders/drivers for display devices.
 Combinational Digital Circuits

Binary Adder: The logic circuits designed to perform the addition of two binary
numbers are called as Binary Adder Circuits
• Half Adder
• Full Adder

Half Adder: A logic circuit for adding two 1-bit numbers, or simply two bits. This
circuit has two inputs and two outputs. The inputs are the two 1-bit binary
numbers, and the outputs are Sum and Carry bits.
Combinational Digital Circuits

A 0 1
B

7486 0 0 1
1 1 0

𝑆𝑢𝑚=𝐴⊕𝐵
7408 A 0 1
B
0 0 0
𝐶0 =𝐴𝐵 1 0 1
 Combinational Digital Circuits

Full Adder (CD 4008 (CMOS)) : A logic circuit for adding two 1-bit numbers, or
simply two bits, with previous input carry. This circuit has three inputs and two
outputs. The inputs are the three 1-bit binary numbers, and the outputs are Sum
and Carry-out bits.

Inputs Outputs
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

𝐶 𝑜𝑢𝑡 = 𝐴 𝐵 𝐶 𝑖𝑛 + 𝐴 𝐵 𝐶 𝑖𝑛 + 𝐴𝐵𝐶 𝑖𝑛 + 𝐴𝐵𝐶𝑖𝑛

Combinational Digital Circuits

AB 00 01 11 10
Cin
0 0 1 0 1
1 1 0 1 0

AB 00 01 11 10
Cin
0 0 0 1 0
1 0 1 1 1
Combinational Digital Circuits

𝐶 𝑜𝑢𝑡 = ( 𝐴 ⊕ 𝐵 ) 𝐶 𝑖𝑛 + 𝐴𝐵
 Combinational Digital Circuits

Half Subtractor: A logic circuit for subtracting two 1-bit numbers, or simply two
bits. This circuit has two inputs and two outputs. The inputs are the two 1-bit
binary numbers, and the outputs are Sum and Carry bits.

𝐷𝑖𝑓𝑓𝑒𝑟𝑒𝑛𝑐𝑒= 𝐴 𝐵+ 𝐴 𝐵= 𝐴⊕ 𝐵
𝐵𝑜𝑟𝑟𝑜𝑤 = 𝐴 𝐵
 Combinational Digital Circuits

Full Subtractor: A logic circuit for subtracting two 1-bit numbers, or simply two
bits, taking into account the previous borrow bit. This circuit has three inputs and
two outputs. The inputs are the two 1-bit binary numbers, and the previous
borrow it, and the outputs are Difference and output-borrow bits.

𝐷= 𝐴 𝐵 𝐵𝑖𝑛 + 𝐴 𝐵 𝐵𝑖𝑛 + 𝐴 𝐵 𝐵𝑖𝑛 + 𝐴𝐵 𝐵𝑖𝑛

𝐵𝑜𝑢𝑡 = 𝐴 𝐵𝑖𝑛 + 𝐴 𝐵 + 𝐵 𝐵𝑖𝑛
Combinational Digital Circuits
 Combinational Digital Circuits

Parallel Binary Adder (74LS83):

• A single full adder adds two one-bit
numbers and an input carry.
• A Parallel Adder is a digital circuit
capable of finding the
arithmetic sum of two binary
numbers that are greater than one
bit in length by operating on
corresponding pairs of bits in
parallel.
• It consists of full adders connected
in a chain where the output carry
from each full adder is connected to
the carry input of the next higher
order full adder in the chain.
• An n-bit parallel adder requires n
full adders to perform the
operation. So for the two-bit
number, two adders are needed
while for four-bit numbers, four
adders are needed, and so on.
 Combinational Digital Circuits

Parallel Binary Subtractor:

• A Parallel Subtractor is a digital circuit capable of finding the arithmetic
difference between two binary numbers that are greater than one bit in length
by operating on corresponding pairs of bits in parallel.
• The parallel subtractor can be designed in several ways: including a
combination of half and full subtractors, all full subtractors, or all full adders
with subtrahend complement input.
 Combinational Digital Circuits

Parallel Binary Adder/ Subtractor:

• The operations of both addition and subtraction can be performed by a one common
binary adder. Such a binary circuit can be designed by adding an Ex-OR gate with
each full adder as shown in figure. The figure shows the 4-bit parallel binary
adder/subtractor which has two 4-bit inputs as ‘A3 A2 A1 A0‘ and ‘B3 B2 B1 B0‘.
• The mode input control line M is connected with the carry input of the least
significant bit of the full adder. This control line decides the type of operation,
whether addition or subtraction.
• When M= 1, the circuit is a subtractor and when M=0, the circuit becomes adder.
The Ex-OR gate consists of two inputs to which one is connected to the B and the other to
input M. When M = 0, B Ex-OR of 0 produces B. Then, full adders add the B with A
with carry input zero and hence an addition operation is performed.
• When M = 1, B Ex-OR of 0 produces B complement and also carry input is 1.
Hence the complemented B inputs are added to A and 1 is added through the input carry,
nothing but a 2’s complement operation.
 Combinational Digital Circuits

Serial Adder:
• Serial binary adder is
a combinational logic
circuit that performs the
addition of two binary
numbers in serial form.
Serial binary adder
performs bit-by-bit
addition.
• Two shift registers are
used to store the binary
numbers that are to be
added.
• A single full adder is used
to add one pair of bits at a
time along with the carry.
• The carry output from the
full adder is applied to a D
flip-flop.
• After that output is used as
a carry for the next
Combinational Digital Circuits
 Combinational Digital Circuits

BCD adder: the 4-bit binary adder IC (7483)

can be used to perform BCD addition.
If the output is not valid BCD code, or, if
carry bit C3 is generated, then 6 (0110) is to
be added to the sum, to get the correct
output.
Q. Subtract 1 from 8
 Combinational Digital Circuits

Carry Look-ahead adder

(74182): Carry has to
propagate along C-1 to C0 to
Cn-1 (LSB to MSB position).
This decreases the speed of
addition.
Hence, a technique called
look-ahead carry is used for
addition.

C0 and S0 (from FA 0) are generated after some propagation delay. Only C0 is

required to propagate upto FA(n-1).
The proper output of FA1 (after its own delay) is generated only after the
propagation delay of FA0, after receiving C0.
Therefore, total delay in FA1 output = delay due to FA0 + delay due to FA1.
Hence, the propagation delay depends on the number of FA stages.
Combinational Digital Circuits
 Combinational Digital Circuits

Now consider a 4-bit adder:

, ,

Fig. a 4-bit adder with look-ahead carry

 Combinational Digital Circuits

Multiplexer: A special combinational

circuit that gates one out of several
inputs to a single output.
• Most widely used standard logic
circuits.
• The input selected is controlled by
the select lines
• For multiplexers with n-input lines,
m-select lines are required for
controlling (n=2m)
• Depending upon the code at the
select inputs, one out of n-inputs is
selected and transferred to the
output channel.
• For operating a multiplexer, an
enable (strobe) input line (G) is +
utilized in the active-low state. At a
high state, the multiplexer outputs
zero.
 Combinational Digital Circuits

The truth table of a 4:1 multiplexer is shown below

Enable Select Output
Input (G) Inputs Y +

0 0 0
0 0 1
0 1 0
0 1 1
1 X X 0
 Combinational Digital Circuits

Q. f(A,B,C,D)= ∑m (0,2,3,6,8,9,12,14)

Enable Select Inputs Output

Input (G) Y

0 0 0 0 0 1
0 0 0 0 1 0
0 0 0 1 0 1
0 0 0 1 1 1
0 0 1 0 0 0
0 0 1 0 1 0
0 0 1 1 0 1
0 0 1 1 1 0
0 1 0 0 0 1
0 1 0 0 1 1
0 1 0 1 0 0
0 1 0 1 1 0
0 1 1 0 0 1
0 1 1 1 0 0
0 1 1 1 1 1
1 X X X X 0
 Combinational Digital Circuits

Demultiplexer: It performs the

reverse of a multiplexer.
• It accepts a single input and
distributes it over several
outputs.
• The select input code
determines to which output
the data input will be
transmitted.
• For demultiplexers with n-
output lines, m-select lines
are required for controlling
(n=2m)
• The data input Di will appear
on the output line selected by
the select input.
• This can also be used as a
binary to decimal decoder.
Combinational Digital Circuits
 Combinational Digital Circuits

PARAMETERS DEMULTIPLEXER DECODER

Definition A demultiplexer is a circuit which takes only one input and A decoder is the circuit which
switches it to one of the several outputs with the help of decodes the input signal fed to it
selection lines. with the help of control signal.

Data Input A demultiplexer accepts the data as input. A decoder accepts control signals
as input.

Number of Inputs Only one One or more signals can be given

as input.

Number of Outputs The output depends on the number of selection lines. The The outputs depends on the
number of outputs will be equivalent to 2 raised to the number of control signals. If there
power of selection lines. If there are n selection lines then are n control signals then the
output will be 2^n. output will be 2^n.

Need of selection lines Required Not required, but control signals

and enable signal is required.

Main Function Used for switching Used for decoding of the encoded
input terminal.
 Combinational Digital Circuits

Popular MSI (Medium scale integration: 500 components (from 10 to less than 100 gates))
IC No. Description Output

74157 Quad 2:1 Multiplexer Same as input

74158 Quad 2:1 Multiplexer Inverted input

74153 Dual 4:1 Multiplexer Same as input

74352 Dual 4:1 Multiplexer Inverted input

74151 8:1 Multiplexer Complementary outputs

74152 8:1 Multiplexer Inverted input

74150 16:1 Multiplexer Inverted input

74139 Dual 1:4 Demultiplexer Inverted input

(2-line to 4-line decoder)
74155 Dual 1:4 Demultiplexer 1 Y-inverted input
(2-line to 4-line decoder) 2 Y- same as input
74138 1:8 Demultiplexer Inverted input
(3-line to 8-line decoder)
74154 1:16 Demultiplexer Same as input
(4-line to 16-line decoder)
 Combinational Digital Circuits

Magnitude comparator (7485 (4-bit)): a

magnitude comparator compares two numbers and
provides outputs depending on the values of the
compared numbers.
The figure shows an n-bit comparator that produces the
output as either A>B, A=B, or, A<B.
The 4-bit comparators are available as MSI IC package
(7485) which can compare binary and BCD codes.

The truth table of a 2-bit comparator is given next

 Combinational Digital Circuits

Inputs Outputs
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
 Combinational Digital Circuits

Parity Generator (74280 (9-bit)): a

A B C D f (Even-parity)
combinational logic circuit that
0 0 0 0 0
generates the parity bit in the
transmitter. The other circuit that checks 0 0 0 1 1
the parity in the receiver is called Parity 0 0 1 0 1
Checker. 0 0 1 1 0
CD 0 1 0 0 1
AB 00 01 11 10
0 1 0 1 0
0 1 1 0 0
00 0 0 0 1 1 1 1
1 0 0 0 1
01 0 0
1 0 0 1 0
11 0 0 1 0 1 0 0
1 0 1 1 1
10 0 0
1 1 0 0 0
1 1 0 1 1
K-map for f’ (POS) 1 1 1 1 0
 Combinational Digital Circuits

In SOP form:
 Combinational Digital Circuits

Parity Checker: a combinational logic circuit for checking the parity

bit of the received codeword.
 Combinational Digital Circuits

Code converter: a combinational logic circuit for converting input

codeword into output codeword, eg. Binary-to-gray, gray-to-binary,
binary-to-BCD, BCD-to-binary, BCD-to-excess3, excess3-to-BCD, etc.
 Combinational Digital Circuits

Priority encoder (74148 8-to-3 line priority encoder):

The priority encoder is a circuit that executes the priority function.
The logic of the priority encoder is such that when two or more inputs
appear simultaneously, the input having the largest priority will
take precedence.
Inputs Outputs Boolean Function

(Interrupt Status)
1 X X X 0 0 1
0 1 X X 0 1 1
0 0 1 X 1 0 1
0 0 0 1 1 1 1
0 0 0 0 X X 0

The truth table of a four-input priority encoder is given in the table. The
X’s in the table designate don’t care conditions. Input has the largest
priority, so indifferent of the values of other inputs when this is input is
1, the output creates an output .
 Combinational Digital Circuits

• I1 has the next priority level. The output is 01 if I1=1 supported

that I0=0, regardless of the values of the other two lower-priority inputs.
• The output for I2 is generated only if higher-priority inputs are 0, etc.
down the priority level.
• The interrupt status IST is set only when one or more inputs are
equal to 1.
• If all inputs are 0, IST is cleared to 0 and the other outputs of the
encoder are not used, so they are signified with don’t care condition.
• This is because the vector address is not shared with the CPU when
IST=0.
• The Boolean function showed in the table determines the internal logic
Generally, a computer will have more than four interrupt sources. A
of the encoder.
priority encoder with eight inputs, for example, will create an output of
three bits.
The output of the priority encoder can form part of the vector address for
each interrupt source. The other bits of the vector address can be created
any value. For instance, the vector address can be formed by joining six
zeroes to the
and outputs of the encoder.
With this choice, the interrupt vector for the four I/O devices is created
 Combinational Digital Circuits

Decoders/drivers for display devices

Used in display devices to view the output, e.g. indicator/relay driver, nixie tube
driver, LED output, seven-segment display, etc.
Combinational Digital Circuits
Combinational Digital Circuits