Digital Electronics (303105220)

Alpita makwana, Assistant Professor

Mechatronics Engineering
 CHAPTER-4

Sequential Circuits

A 1-bit memory, the circuit properties of Bi-stable latch, the clocked SR flip flop, J- K-
T and D types flip flops, applications of flip flops, shift registers, applications of shift
registers, ring counter, sequence generator, ripple (Asynchronous) counters,
synchronous counters, special counter IC’s, asynchronous sequential counters,
applications of counters.
 Sequential Circuits

Sequential circuits are digital circuits that store and use the
previous state information to determine their next state.
Unlike combinational circuits, which only depend on the current input
values to produce outputs, sequential circuits depend on both the
current inputs and the previous state stored in memory elements.
1. Sequential circuits are commonly used in digital systems to
implement state machines, timers, counters, and memory
elements.
2. The memory elements in sequential circuits can be implemented using
flip-flops, which are circuits that store binary values and maintain
their state even when the inputs change.
 Sequential Circuits
Flip-flop: Another name for bistable multivibrator. Used for storing a single bit
(memory element)
State of FF: State of Q
𝑸 Normal output
State of FF:
Inputs

FF High/1/SET , for Q=1

Low/0/RESET, for Q=0
𝑸 Inverted output

• The inputs cause change in output state (Flip-Flop)

• FF input is applied temporarily to change its output state.
• Input applied in form of pulses.
• The output now remains in new state, even when input is removed (Memory)
• Used to store 1-bit of data.
• Basic component of shift-registers and counters.

*Non-clocked FF is called Latch Latch: Level-triggered

FF: Edge-triggered
 Sequential Circuits

• A Flip Flop is a memory element that is capable of storing one bit of information.
• It is also called as a Bistable Multivibrator since it has two stable states either
0 or 1.
Sequential Circuits

Using NOR gates

Using NAND gates
 Sequential Circuits
Bistable Latch/RS Flip-flop: Circuit properties
Case I: Case II:

𝑄=0 𝑄=1 𝑄=1 𝑄=0

𝑄=1 𝑄=0 𝑄=0 𝑄=1

NAND-GATES
 Sequential Circuits
Bistable Latch/RS Flip-flop: Circuit Properties
• The outputs and are always complementary.
• The circuits has two stable states. One state is (Set state),
Another is (Reset state).
• The circuits continues to be in the same state, zero or one.

How to store the desired bit ?

Used to enter desired bit

NOR-GATES
 Sequential Circuits

0 0 1
0 1 1
1 0 1
1 1 0

Case I: Input to Input to Output of

G1 G2 G2 (
0 1,0 1 0 1,1 0
Case II: Input to Input to Output of
G1 G2 G2 (
0 1,1 0 0 1,0 1
 Sequential Circuits

0 0 1
0 1 1
1 0 1
1 1 0

Case I: Input to Input to Output of

G1 G2 G2 (
1 0,0 1 0 1,1 0
Case II: Input to Input to Output of
G1 G2 G2 (
1 0,1 1 0 1,1 0
 Sequential Circuits

SR 00 01 11 10
Remarks
0 X 1 0 0 No change
1 1 X 1 0 1 0 1 reset condition
1 0 1 0 set condition
Characteristic eq. of SR-FF:
1 1 Not valid Not valid Invalid combination
𝑸 𝒏+𝟏 =𝑺+𝑸 𝒏 𝑹

𝑆 NAND 𝑄 𝑅 NOR 𝑄
Sequential Circuits
Clocked RS flip flop

Inputs
Output
Clock Clear Preset Q Operation
(CK) (Cr) (Pr)
1 1 1 Qn+1 Normal FF
0 0 1 0 Clear
0 1 0 1 Preset
 Sequential Circuits
JK- flip flop
Remarks
………………………. 0 0 0
1 1 Not valid Not valid Invalid 0 1 0
combination
1 0 0
Data Outputs Inputs to SR Output
inputs FF 1 1 1

0 0 0 1 0 0 0 (=)
0 0 1 0 0 0 1 (=)
1 0 0 1 1 0 1
1 0 1 0 0 0 1
0 1 0 1 0 0 0
0 1 1 0 0 1 0
1 1 0 1 1 0 1 (=)
1 1 1 0 0 1 0 (=)
 Sequential Circuits
Inputs Output JK- flip flop

00 01 11 10
0 0 0 0 0 1 1
0 1 0 1 1 0 0 1
1 0 1
1 1
𝑸 𝒏+𝟏 =𝑸𝒏 𝑱 +𝑸 𝒏 𝑲
 Sequential Circuits
Race-around condition
Inputs Output
∆𝒕
0 0
0 1 0
1 0 1 𝑻𝒑
1 1 𝟎 𝑻
Trailing (negative) edge

Leading (positive) edge

The propagation delay through two NAND gates in series.
Output oscillates after every when the clock pulse () is high,
when both JK inputs are high.
• At the end of clock pulse, the output is not certain.
Avoided, if is made smaller than . Practical method - use Master Slave flip flop
 Sequential Circuits

Master-Slave Flip-flop (Pulse triggered FF)

• The Race-around Condition can be avoided by ensuring that the

clock input is at logic “1” only for a very short time.
• The Master-Slave Flip-Flop is a combination of two JK flip-flops
connected in a series configuration.
• One acts as the “master” and the other as a “slave”.
• The output from the master flip-flop is connected to the two inputs
of the slave flip flop whose output is fed back to the inputs of the
master flip-flop.
• In addition to these two flip-flops, the circuit also includes
an inverter.
• The inverter is connected to the clock pulse in such a way that the
inverted clock pulse is given to the slave flip-flop. In other words if
CLK=0 for a master flip-flop, then CLK=1 for a slave flip-flop, and if
CLK=1 for a master flip flop then it becomes 0 for a slave flip-flop.
 Sequential Circuits

Master-Slave Flip-flop (Pulse triggered FF)

 Sequential Circuits
D (Delay) flip flop

Inputs Output 𝑪𝒉𝒂𝒓𝒂𝒄𝒕𝒆𝒓𝒊𝒔𝒕𝒊𝒄 𝑬𝒒 .:𝑸 𝐧 +𝟏= 𝑫

0 0
0 1
0 1 0
0 0 1
1 0 1
1 0 1
1 1 1

Characteristic Table of D-FF

 Sequential Circuits
D flip flop: From SR flip flop S

0 0 0 0 X
0 1 0 0 1
1 0 1 1 0
1 1 1 X 0 R

0 1 0 1
0 0 1 0 X 0
Characteristic Table Excitation table 1 0 X 1 1 0
of D-FF of SR-FF

𝑺=𝑫 𝑹=𝑫
 Sequential Circuits
D flip flop: From JK flip flop J

0 0 0 0 X
0 1 0 X 1
1 0 1 1 X
1 1 1 X 0 K

0 1 0 1
0 0 1 0 X X
Characteristic Table Excitation table 1 X X 1 1 0
of D-FF of JK-FF

𝑱=𝑫 𝑲=𝑫
 Sequential Circuits
T (Toggle) flip flop
Inputs Output
𝑪𝒉𝒂𝒓𝒂𝒄𝒕𝒆𝒓𝒊𝒔𝒕𝒊𝒄 𝑬𝒒 .:𝑸 𝐧 +𝟏=𝑻 𝑸 𝒏 +𝑻 𝑸𝒏 =𝑻 ⊕ 𝑸𝒏
0 0 0 1
0 1 1 0 0 1
1 0 1 1 1 0
1 1 0

Characteristic Table of T-FF

 Sequential Circuits
T flip flop: From JK flip flop

0 0 0 0 X
0 1 1 X 0
1 0 1 1 X
1 1 0 X 1
0 1 0 1
0 0 1 0 X X
Characteristic Table Excitation table 1 X X 1 0 1
of T-FF of JK-FF

𝑱 =𝑻 𝑲 =𝑻
 Sequential Circuits
Excitation Tables of FFs:

Flip-flop conversion
 Sequential Circuits
Timing diagrams of FFs:
Q: Consider the following Clock and Input waveforms to the FF.

Sketch the output waveforms for the following FFs:

a) Positive-edge triggered D-type FF 74 AHC74.
b) Positive-level triggered D-type FF 7475.
c) Negative-edge triggered JK-Flip flop 74HC112.
 Sequential Circuits
Positive-edge

Positive-level Negative-edge
 Sequential Circuits

(Positive-edge
Triggered)

(Positive-level
Triggered)

(Negative-edge
triggered)
 Sequential Circuits
Applications of flip flop:

• Frequency dividers
• Counters
• Storage registers
• Shift registers
• Data storage
• Bounce elimination switch
• Latch
• Data transfer
• Memory
• Registers
 Sequential Circuits
Shift Registers:
A Register is a device that is used to store such information.
Intel's 8085 processor contains many 8-bit registers for storage and result
purposes,
It is a group of flip-flops connected in series used to store multiple bits of data.
The information stored within these registers can be transferred with the help
of shift registers.
Shift Register is a group of flip flops used to store multiple bits of data. The
bits stored in such registers can be made to move within the registers and in/out
of the registers by applying clock pulses.
An n-bit shift register can be formed by connecting n flip-flops, where each
flip-flop stores a single bit of data.
The registers which will shift the bits to the left are called Shift-left registers.
The registers which will shift the bits to the right are called Shift-right
registers
 Sequential Circuits
Data can be entered and retrieved in following forms:
a) Serial-In Serial-out
b) Serial-in Parallel-out
c) Parallel-in serial-out
d) Parallel-in parallel-out

A 3-bit shift-register using 7474 positive-edge triggered FF

Sequential Circuits
 Sequential Circuits
Shift Register Application - Ring Counter:
• Typical application of the Shift register.
• The output of the last flip-flop is connected to the input of the first flip-flop in
the case of the ring counter but in the case of the shift register it is taken as
output.
• Except for this, all the other things are the same.

Clock (-ve
Edge-Triggered)

Overriding Input
 Sequential Circuits

The clock pulse (CLK) is simultaneously applied to all the flip-flops. (Synchronous
Counter)
Also, here we use Overriding input (ORI) for each flip-flop - Preset (PR) and Clear
(CLR) are used as ORI.
When PR is 0, then the output is 1, and when CLR is 0, then the output is 0.
PR and CLR are active low signals that always work in value 0.

PR = 0, Q = 1; CLR= 0, Q = 0
 Sequential Circuits

• ORI is connected to Preset (PR) in

FF-0 and it is connected to Clear
(CLR) in FF-1, FF-2, and FF-3.
• Output Q = 1 is generated at FF-0,
and the rest of the flip-flop
generates output Q = 0.
• This output Q = 1 at FF-0 is known
as Preset 1, which is used to form
Preset 1
the ring in the Ring Counter.

Counter states (modulo-n)

ORI CLK Q0 Q1 Q2 Q3
0 X 1 0 0 0

1 0 0 1 0 0

1 0 0 0 1 0

1 0 0 0 0 1

1 0 1 0 0 0
 Sequential Circuits

ORI CLK Q0 Q1 Q2 Q3

0 X 1 0 0 0
1 0 1 1 0 0
Johnson’s counter 1 0 1 1 1 0
Counter states
• Counts 2*n states
1 0 1 1 1 1
(modulo-2n)
1 0 0 1 1 1

1 0 0 0 1 1

1 0 0 0 0 1

1 0 0 0 0 0

1 0 1 0 0 0
 Sequential Circuits

STRAIGHT RING COUNTER TWISTED RING COUNTER

It connects the complement of output of the

It connects the output of the last shift register last shift register to the input of the first
to the input of first shift register. register.

It is known as Walking ring counter or Johnson’s

It is known as One hot counter. counter.

Number of states = number of flip-flops Number of states = 2 x number of flip-flops

It circulates stream of 1 followed by stream of

It circulates a single bit (0 or 1) around the ring. 0.

PRESET is used in first shift register. PRESET is not used in twisted ring counter.

CLEAR is used for last (n-1) flip-flops. CLEAR is used for all flip-flips in it.

It is used in successive approximation and It is used in phase shift or function generator.

stepper motor control.
 Sequential Circuits

• Shift registers are also utilized in Sequence generator circuits

• Sequence generator: generates a given sequence of bits (in synchronism with a clock)

𝑌 = 𝑓 (𝑄 𝑁 −1 , 𝑄 𝑁 − 2 , …, 𝑄1 , 𝑄0 )

The minimum no. of FFs (N) required to generate a sequence of length S-

 Sequential Circuits

Q: Generate a sequence …1101011…

The minimum no. of FFs (N) required to generate a sequence of length 7: . So,

No. of Flip-flop outputs

clock pulses

1 1 1 1 Same states ⟹ 𝑁>3

2 1 1 1
⟹ 𝑁 =4
3 0 1 1
4 1 0 1
5 0 1 0
6 1 0 1
7 1 1 0
. . . .
. . . .
 Sequential Circuits

Q: Generate a sequence …1101011… 𝑵 =𝟒

No. of Flip-flop outputs Serial input
clock pulses Y

1 1 1 1 0 1
2 1 1 1 1 0
3 0 1 1 1 1
4 1 0 1 1 0
Diff.
5 0 1 0 1 1
states
6 1 0 1 0 1
7 1 1 0 1 1
1 1 1 1 0 1
2 1 1 1 1 0
3 0 1 1 1 1
 Sequential Circuits

Q: Generate a sequence …1101011…

00 01 11 10

00 X X X X
01 X 1 1 X
11 X 1 0 0
10 X X 1 1

𝑄 3 𝑄1 𝑄 0

𝑌 =𝑄 3 +𝑄 1+ 𝑄0
 Sequential Circuits
Counters:
• Asynchronous (ripple counter): All FFs not clocked simultaneously
• Synchronous (Ring: modulo-n, Twisted ring: modulo-2n) counter: All FFs clocked
simultaneously
However, total possible states with n-FFs:
up-counter ) counter is possible
Counter Count
state up-counter & down-counter

0 0 0 0 changes from 0 to 1
1 0 0 1 changes from 1 to 0, changes from 0 to 1
2 0 1 0
3 0 1 1 changes from 1 to 0, changes from 1 to 0,
4 1 0 0 changes from 0 to 1
5 1 0 1 changes with every clock pulse
6 1 1 0 changes with every 2-clock pulses
changes with every 4-clock pulses
7 1 1 1
 Sequential Circuits
Design Procedure:
• Q0 needs to change with every clock pulse.
So, the input to FF0 is T0=1, and the external clock is provided to FF 0.
• Q1 toggles when Q0 goes from 1 to 0.
It means that the Negative edge of Q0 toggles Q1. So we can use Q0 as the clock input for FF1.
• Q2 toggles when Q1 goes from 1 to 0 (negative edge).
This is used as a clock signal for FF2.

A 3-bit binary counter

 Sequential Circuits

0 1 0 1 0
0 1 0 1

1 1
0 0 0 0 1 1 0

0 0 0 0 1 1 1 1 0
 Sequential Circuits
Q. Design a mod-5 synchronous up counter using J-K flip flop

0 0 0
0 0 1 Desired states 0 0 0 X
0 1 0 0 1 1 X
0 1 1 1 0 X 1
1 0 0 1 1 X 0
1 0 1
Excitation table of JK FF
1 1 0
1 1 1
 Sequential Circuits
Q. Design a mod-5 synchronous up counter using J-K flip flop

Present state Next state Flip flop inputs

0 0 0
Desired states

0 0 1
0 0 0 0 0 1 0 X 0 X 1 X
0 1 0
0 0 1 0 1 0 0 X 1 X X 1
0 1 1
0 1 0 0 1 1 0 X X 0 1 X
1 0 0
0 1 1 1 0 0 1 X X 1 X 1
1 0 1
1 0 0 0 0 0 X 1 0 X 0 X
1 1 0
1 0 1 X X X X X X X X X
1 1 1
1 1 0 X X X X X X X X X
1 1 1 X X X X X X X X X

Excitation table for mod-5 counter

 Sequential Circuits
00 01 11 10 00 01 11 10
0 0 0 x x 0 x x x 1
1 0 1 x x 1 x x x x

𝐽 𝑐 =𝑄 𝑎 𝑄 𝑏 𝐾 𝑐 =1
00 01 11 10 00 01 11 10
0 0 x x 0 0 x 0 1 x
1 1 x x x 1 x x x x

𝐽 𝑏=𝑄 𝑎 𝐾 𝑏=𝑄𝑐
00 01 11 10 00 01 11 10
0 1 1 x 0 0 x x x x
1 x x x x 1 1 1 x x

𝐽 𝑎=𝑄 𝑐 𝐾 𝑎=1
 Sequential Circuits
𝑱 𝒄 =𝑸 𝒂 𝑸 𝒃 𝑲 𝒄 =𝟏 𝑱 𝒃=𝑸 𝒂𝑲 𝒃=𝑸 𝒄 𝑱 𝒂 =𝑸 𝒄𝑲 𝒂 =𝟏

𝐽𝑎 𝑄𝑎 𝐽𝑏 𝑄𝑏 𝐽𝑐 𝑄𝑐

𝐾𝑎 𝑄𝑎 𝐾𝑏 𝑄𝑏 𝐾𝑐 𝑄𝑐
CLK
Logic “1”

mod-5 synchronous up-counter using J-K flip

flop
 Sequential Circuits
Special counter ICs:
• 74HC161
• 74HC163
• 74HC191
• 74HC160
• CD4017B

Applications of counters:
• Pulse counting
• Frequency division
• Digital clocks
• Analog-to-digital converters