Processor Fundamentals As
Processor Fundamentals As
Fundamentals
CPU Architecture
• In the Von Neumann architecture, system buses (address bus, data bus, and control bus) are used for parallel data
transmission, with each wire transmitting one bit of data.
• Address bus
• The address bus is unidirectional, carrying memory addresses from the CPU to other components, preventing
addresses from being sent back to the CPU.T
• he width of the address bus determines the number of memory locations that can be addressed, with wider
buses allowing access to more memory locations (e.g., 16-bit can address 65,536 locations, while 32-bit can
address over 4 billion).
• Data bus
• The data bus is bidirectional, allowing data (including addresses, instructions, or numerical values) to be transferred
between the CPU, memory, and input/output devices.
• The width of the data bus determines the word length that can be transported, with larger word lengths (e.g., 16-bit,
32-bit, 64-bit) improving the computer's overall performance.
• Control bus
• The control bus is bidirectional and carries control signals from the Control Unit (CU) to other computer components.
• It also transmits timing signals to synchronize operations, with the system clock determining the clock cycle and
overall processing speed.
• Clock speed affects processing speed, but increasing it doesn't always guarantee better performance. Overclocking can
cause instability or overheating, as the system might exceed its design limits.
• Cache memory, using faster SRAM, stores frequently accessed instructions, improving processor performance by
reducing reliance on slower main memory.
• Multiple cores (e.g., dual or quad core) can enhance performance by parallel processing, but communication between
cores and the CPU reduces the overall speed improvement.
• In summary increasing bus width (data and address buses) increases the performance and speed of a computer
system
• increasing clock speed usually increases the speed of a computer
• a computer’s performance can be changed by altering bus width, clock speed and use of multi-core CPUs
• use of cache memories can also speed up a processor’s performance.
• Computer ports
• Input and output devices are connected to a computer via ports. The interaction of the ports with connected
input and output is controlled by the control unit.
• USB ports
• USB uses a four-wire cable, with two for power and earth, and two for data transmission.
• When a device is connected, the computer automatically detects it by sensing a voltage change in the data signal
wires.
• The computer then either loads the appropriate device driver or prompts the user to download it if it's not
available.
• High-definition multimedia interface (HDMI)
• HDMI ports provide high-definition audio and visual output, replacing the older VGA analogue system with digital
signals.
• Modern HD televisions require higher data rates (around 10 Gbps) due to their widescreen format, higher pixel
counts (e.g., 1920 × 1080), faster refresh rates, and a wide color range.
• HDMI includes high-bandwidth digital copy protection (HDCP), which authenticates connected devices to prevent
piracy before data transmission occurs.
• Video Graphics Array (VGA)
• VGA, introduced in the late 1980s, supports a resolution of 640 × 480 pixels at a refresh rate of up to 60 Hz with a
maximum of 16 colors.
• Reducing the pixel density to 200 × 320 allows VGA to support up to 256 colors.
• The technology is analogue and, as mentioned in the previous section, is being phased out.
• Fetch-execute cycle
• In the fetch-execute cycle, the processor fetches data and instructions from memory using the address and data
buses, stores them in registers, decodes each instruction, and then executes them.
• Fetch
• The next instruction is fetched from the memory address in the program counter (PC) and stored in the current
instruction register (CIR), after which the PC is incremented to point to the next instruction.
• The fetched instruction is then decoded for interpretation in the next part of the fetch-execute cycle.
• Execute
• The processor sends the decoded instruction as control signals to the relevant components, enabling the
execution of each instruction in the correct logical sequence.
• Use of interrupts in the fetch-execute cycle
• The interrupt register monitors status changes during the fetch-execute cycle, allowing the CPU to respond to
interrupts that occur mid-cycle.
• When an interrupt is detected (e.g., indicated by a bit change), the CPU checks the interrupt register and
determines whether to service it based on priority.
• If servicing the interrupt is necessary, the CPU stops its current task, saves the contents of its registers, and
transfers control to the interrupt handler (ISR).
• After the interrupt is serviced, the interrupt register is reset, and the CPU restores the previous contents of its
registers to resume normal operation.
• Interrupts
• Interrupts are signals from devices or software that prompt the processor to temporarily halt its current task to
address the interrupt, which can arise from timing signals, I/O processes, hardware faults, user interactions, or
software errors.
• Upon receiving an interrupt, the processor must identify the interrupt type and priority level before deciding
whether to service the interrupt or continue with the current task.
• When servicing an interrupt, the CPU saves the status of the interrupted task, executes the interrupt service
routine (ISR), and then restores the saved status to resume the original task from where it left off.
• Assembly Language and Machine Code
• Machine code is the only language a CPU can directly use, consisting of binary instructions specific to each type of
chip, and is often displayed in hexadecimal for easier human understanding.
• Writing programs in machine code is complex, time-consuming, and error-prone, requiring direct testing through
execution.
• Assembly language was developed as an easier alternative, using mnemonics to represent machine code, and
requires translation before being executed by the CPU.
• Both assembly language and machine code instructions have the same structure, consisting of an opcode and
often an operand.
• The opcode specifies the CPU operation, while the operand typically identifies the data or memory location for
that operation.
• Stages of Assembly
• Assemblers translate assembly language programs into machine code and check for syntax errors to ensure valid
opcodes are used.
• Single pass assemblers directly place machine code instructions into memory for immediate execution.
• Two pass assemblers generate an object program that can be stored and executed later, using a loader to handle
the machine code and memory address replacement.
• Two pass assemblers need to scan the source program twice, so they can replace labels in the assembly program
with memory addresses in the machine code program.
• Assembly language instructions
• Data movement instructions: These instructions allow data stored at one location to be copied into the
accumulator. This data can then be stored at another location, used in a calculation, used for a comparison or
output.
• LDM(Load Memory)
• LLD(Load Lower Data)
• LDI(Load Immediate)
• LDX(Load Index)
• LDR(Load Register)
• LDR(ACC)
• MOV(Move)
• STO(Store)
• END(End)