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Slide 10 (ARM Core Data Flow Model and 3 Stage Pipelining)

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27 views25 pages

Slide 10 (ARM Core Data Flow Model and 3 Stage Pipelining)

Uploaded by

gsingh20be20
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© © All Rights Reserved
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Pipelining (3 Stage)

Slides are borrowed from the NPTEL Course “ ARM Based Development”
Pipelining Definition
Introduction
The organization of the ARM integer processor core
changed very little from the first 3 micron devices
developed at Acorn Computers between 1983 and 1985
to the ARM6 and ARM7 developed by ARM Limited
between 1990 and 1995.
Contd…
The 3-stage pipeline used by these processors was
steadily tightened up, and CMOS process technology
reduced in feature size by almost an order of
magnitude over this period, so the performance of
the cores improved dramatically, but the basic
principles of operation remained largely the same.
Contd….
Since 1995 several new ARM cores have been
introduced which deliver significantly higher
performance through the use of 5-stage pipelines and
separate instruction and data memories (usually in the
form of separate caches which are connected to a shared
instruction and data main memory system).
3 stage pipeline ARM organization
The principal components are:
 The register bank, which stores the processor state.

 It has two read ports and one write port which can each be

used to access any register, plus an additional read port and


an additional write port that give special access to r15, the
program counter.
 The additional write port on r15 allows it to be updated as

the instruction fetch address is incremented and the read


port allows instruction fetch to resume after a data address
has been issued.
The principal components are:
contd…
 The barrel shifter, which can shift or rotate one operand by any

number of bits.
 The ALU, which performs the arithmetic and logic functions required

by the instruction set.


 The address register and incrementer, which select and hold all

memory addresses and generate sequential addresses when required.


 The data registers, which hold data passing to and from memory.

 The instruction decoder and associated control logic.


 In a single-cycle data processing instruction, two register

operands are accessed, the value on the B bus is shifted and


combined with the value on the A bus in the ALU, then the
result is written back into the register bank.

 The program counter value is in the address register, from

where it is fed into the incrementer, then the incremented


value is copied back into rl5 in the register bank and also
into the address register to be used as the address for the next
instruction fetch.
The 3 stage pipeline
ARM employ a simple 3-stage pipeline with the following
pipeline stages:
 Fetch
the instruction is fetched from memory and placed in the
instruction pipeline.
 Decode
the instruction is decoded and the datapath control signals
prepared for the next cycle. In this stage the instruction 'owns'
the decode logic but not the datapath.
 Execute
the instruction 'owns' the datapath; the register bank is read, an
operand shifted
References
1. ARM System on Chip Architecture, Second Edition,
Steve Furber.

2. Video Lectures of Prof. Mouli Sankaran on ARM


Based Development.
https://nptel.ac.in/courses/117106111/

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