Remaining portion of the syllabus

ARM Block diagram

ARM core data flow model
ARM core data flow model…….contd
 Architecture versions and variants

Dr. Shireesh Kumar Rai

Assistant Professor, ECED
Thapar Institute of Engineering and Technology, Patiala

Email:[email protected]
Architecture versions and variants
 The ARM instruction set architecture has evolved significantly

since it was first developed, and will continue to be developed in

the future.

 In order to be precise about which instructions exist in any

particular ARM implementation, five major versions of the

instruction set have been defined to date.

 These are denoted by the version numbers 1 to 5.

Version 1
 This version was implemented only by ARM1, and was never used in a

commercial product.
 It contained:

1. the basic data-processing instructions (not including multiplies)

2. byte, word, and multi-word load/store instructions

3. branch instructions, including a branch-and-link instruction designed

for subroutine calls

4. a software interrupt instruction, for use in making Operating System

calls.

5. Version 1 only had a 26-bit address space, and is now obsolete.

Version 2
This version extended architecture version 1 by adding:

1. multiply and multiply-accumulate instructions

2. coprocessor support

3. two more banked registers in fast interrupt mode

4. atomic load-and-store instructions called SWP and SWPB

(in a slightly later variant called version 2a).

5. Versions 2 and 2a still only had a 26-bit address space,

and are now obsolete.
Version 3
1. This architecture version extended the addressing range to 32 bits.

2. Program status information which had previously been stored in R15 was

moved to a new Current Program Status Register (CPSR), and Saved

Program Status Registers (SPSRs) were added to preserve the CPSR

contents when an exception occurred.

3. As a result, the following changes occurred to the instruction set:

 two instructions (MRS and MSR) were added to allow the new CPSR and

SPSRs to be accessed.

 the functionality of instructions previously used to return from exceptions was

modified to allow them to continue to be used for that purpose.

Version 3 contd…

 Version 3 also added two new processor modes in order to make

it possible to use Data Abort, Prefetch Abort and Undefined

Instruction exceptions effectively in Operating System code.

 Backwards-compatibility support for the 26-bit architectures

was obligatory in version 3,except in a variant called version

3G. The distinction between versions 3 and 3G is now obsolete.
Version 4
This version extended architecture version 3 by adding:
1. half word load/store instructions
2. instructions to load and sign-extend bytes and half words
3. in T variants, an instruction to transfer to Thumb state
4. a new privileged processor mode that uses the User mode
registers.
5. Version 4 also made it clearer which instructions should
cause the Undefined Instruction exception to be taken.
6. Backwards-compatibility support for 26-bit architectures
ceased to be obligatory in version 4.
Version 5
This version extends architecture version 4 by adding
instructions and slightly modifying the definitions of some
existing instructions to:

improve the efficiency of ARM/Thumb interworking in T

variants
allow the same code generation techniques to be used for

non-T variants as for T variants.

Version 5 contd…
Version 5 also:
 adds a count leading zeros instruction, which (among
other things) allows more
 efficient integer divide and interrupt prioritization
routines
 adds a software breakpoint instruction
 adds more instruction options for coprocessor
designers
 tightens the definition of how flags are set by multiply
instructions.
The Thumb instruction set (T variants)

 The Thumb instruction set is a re-encoded subset of the

ARM instruction set.

 Thumb instructions are half the size of ARM instructions

(16 bits compared with 32), with the result that greater
code density can usually be achieved by using the Thumb
instruction set instead of the ARM instruction set.
The Thumb instruction set (T
variants)

Two limitations of the Thumb instruction set compared with the

ARM instruction set are:

 Thumb code usually uses more instructions for the same job,
so ARM code is usually best for maximizing the performance
of time-critical code.

 The Thumb instruction set does not include some instructions

that are needed for exception handling, so ARM code needs to
be used for at least the top-level exception handlers.
The Thumb instruction set (T variants) cont.….

1. Because of the second of these, the Thumb

instruction set is always used in conjunction with a

suitable version of the ARM instruction set.

2. Its presence is denoted by the variant letter T, and it

is not valid prior to ARM architecture version 4.

Thumb instruction set versions
There are two versions of the Thumb instruction set:
1. Thumb version 1 is used in T variants of ARM architecture version 4

2. Thumb version 2 is used in T variants of ARM architecture version 5.

Compared with Thumb version 1, Thumb version 2:

3. adds instructions and slightly modifies the definition of some existing

instructions to improve the efficiency of ARM/Thumb interworking

4. adds a software breakpoint instruction

5. tightens the definition of how the Thumb multiply instruction sets the
flags.
 These improvements are closely related to the changes between ARM

architecture versions 4 and 5.

Long multiply instructions (M variants)

 M variants of the ARM instruction set include four extra

instructions which perform 32 x 32 64

 multiplications and 32 x 32 + 64 64 multiply-accumulates.

These instructions imply the existence of a

 multiplier that is significantly larger than minimum, and so are

sometimes omitted in implementations for which a small die size

is very important and multiply performance is not very important.
Their presence is denoted by the use of the variant letter M.
Enhanced DSP instructions (E variants)
 E variants of the ARM instruction set include a number of extra instructions

which enhance the performance of an ARM processor on typical digital signal

processing (DSP) algorithms.

 Several new multiply and multiply-accumulate instructions that act on 16-bit

data items

 Addition and subtraction instructions that perform saturated signed

arithmetic.

 This is a form of integer arithmetic that produces the maximum negative or

positive value instead of wrapping around if the calculation overflows the

normal integer range.

Enhanced DSP instructions (E variants)….contd

Load (LDRD), store (STRD) and coprocessor register

transfer (MCRR and MRRC) instructions that act on 2

words of data.

A cache preload instruction PLD.

The ARMv5TExP architecture version
 Some early implementations of the enhanced DSP variant of the ARM

architecture omitted the LDRD, STRD, MCRR, MRRC and PLD

instructions.

 Apart from this omission, all the ARM implementations concerned

implemented the ARMv5TE architecture.

 In order to be able to name this architecture variant, the letter P can be used

to exclude these five instructions from architecture version ARMv5TE,

according to the rules in Naming of ARM/Thumb architecture versions on
page viii. The resulting architecture variant is therefore named ARMv5TExP.
Naming of ARM/Thumb architecture versions

 To name a precise version and variant of the ARM/Thumb architecture, the

following strings are concatenated:

1. The string ARMv.

2. The version number of the ARM instruction set.

3. Variant letters of the included variants, except that the M variant is standard
in architecture versions 4 and above, and therefore not normally listed.

4. If any variants described as standard in 3 above are not present, the letter x
followed by the letter of the excluded variants. In addition, the letter P can be
used after x to denote the exclusion of certain instructions from architecture
version ARMv5TE, as described in The ARMv5TExP architecture version.
ARM 7TDMI
 The ARM7TDMI (ARM7+ 16 bit Thumb+ JTAG Debug + fast Multiplier +
enhanced ICE) processor implements the ARMv4 instruction set. It was licensed
for manufacture by an array of semiconductor companies.
 In 2009 it was one of the most widely used ARM cores, and is found in numerous
deeply embedded system designs.

 The Joint Test Action Group (JTAG) is an electronics industry association

formed in 1985 for developing a method of verifying designs and testing
printed circuit boards after manufacture.

 It is a versatile processor designed for mobile devices and other low power
electronics. This processor architecture is capable of up to 130 MIPS on a typical
0.13 µm process. The ARM7TDMI processor core implements ARM architecture
v4T.

 The processor supports both 32-bit and 16-bit instructions via the ARM and
Thumb instruction sets.
ARM Family Attribute Comparison
 Addressing Modes

Data Processing Operands

There are 11 addressing modes used to calculate the <op1>
in an ARM data-processing instruction.

The general instruction syntax is:

opcode <cc> <S> Rd, Rn, <op1>

 2. Memory Access
There are nine addressing modes used to calculate the
address for a Load and Store Word or Unsigned Byte
instruction.
The general instruction syntax is: