Digital Design

With an Introduction to the Verilog HDL, VHDL, and

SystemVerilog
6th Edition

Chapter 03
Gate-Level Minimization

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Figure 3.1
Two-variable K-map.

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Figure 3.2
Representation of functions in the K-map.

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Figure 3.3
Three-variable K-map.

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Figure 3.4
Map for Example 3.1, F(x, y, z) = 𝚺(2, 3, 4, 5) = x’y + xy’.

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Figure 3.5
Map for Example 3.2, F(x, y, z) = 𝚺(3, 4, 6, 7) = yz + xz’.

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Figure 3.6
Map for Example 3.3, F(x, y, z) = 𝚺(0, 2, 4, 5, 6) = z’ + xy’.

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Figure 3.7
Map of Example 3.4, A’C + A’B + AB’C + BC = C + A’B.

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Figure 3.8
Four-variable map.

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Figure 3.9
Map for Example 3.5, F(w, x, y, z) = 𝚺(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) =
y’ + w’z’ + xz’.

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Figure 3.10
Map for Example 3.6, A’B’C’ + B’CD’ + A’BCD’ + AB’C = B’D’ + B’C’ +
A’CD’.

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Figure 3.11
Simplification using prime implicants.

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Figure 3.12
Map for Example 3.7, F(A, B, C, D) = 𝚺(0, 1, 2, 5, 8, 9, 10) = BD + BC +
ACD = (A’ + B’)(C’ + D’)(B’ + D).

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Figure 3.13
Gate implementations of the function of Example 3.7.

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Table 3.1
Truth Table of Function F.

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Figure 3.14
Map for the function of Table 3.1.

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Practice Exercise 3.8

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Figure 3.15
Example with don’t-care conditions.

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Figure 3.16
Logic operations with NAND gates.

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Figure 3.17
Two graphic symbols for a three-input NAND gate.

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Figure 3.18
Three ways to implement F = AB + CD.

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Figure 3.19
Solution to Example 3.9.

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Practice Exercise 3.10

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Figure 3.20
Implementing F = A(CD + B) + BC’.

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Figure 3.21
Implementing F = (AB’ + A’B)(C + D’).

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Figure 3.22
Logic operations with NOR gates.

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Figure 3.23
Two graphic symbols for the NOR gate.

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Figure 3.24
Implementing F = (A + B)(C + D)E.

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Figure 3.25
Implementing F = (AB’ + A’B)(C + D’) with NOR gates.

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Practice Exercise 3.11

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Figure 3.26
Wired logic
(a) Wired-AND logic with two NAND gates
(b) Wired-OR in emitter-coupled logic (ECL) gates.

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Figure 3.27
AND–OR–INVERT circuits, F = (AB + CD + E)’.

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Figure 3.28
OR–AND–INVERT circuits, F = [(A + B)(C + D)E]’.

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Table 3.2
Implementation with Other Two-Level Forms.

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Figure 3.29
Other two-level implementations.

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Figure 3.30
Logic diagrams for exclusive-OR implementations.

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Figure 3.31
Map for a three-variable exclusive-OR function.

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Figure 3.32
Logic diagram of odd and even functions.

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Figure 3.33
Map for a four-variable exclusive-OR function.

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Table 3.3
Even-Parity-Generator Truth Table.

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Figure 3.34
Logic diagram of a parity generator and checker.

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Table 3.4
Even-Parity-Checker Truth Table.

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Figure 3.35
A logic diagram (schematic) for the Boolean equations D = A + B E =
CD.

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Figure PE3.12

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Figure 3.36
Entity-Architecture pair for or_and_vhdl.

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Figure PE3.13

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Figure 3.37
Schematic for and_or_prop_delay.

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Table 3.5
Output of Gates after Delay.

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Figure 3.38
Simulation waveforms of and_or_prop_delay.

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Figure 3.39
Entity-architecture for a structural model of
and_or_prop_delay_vhdl.

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Table 3.6
Logic Symbols of the IEEE_std_logic_1164 Package.

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Figure 3.40
Schematic for Circuit with_UDP_02467.

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Figure P3.38

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