Digital Design

With an Introduction to the Verilog HDL, VHDL, and

SystemVerilog
6th Edition

Chapter 05
Synchronous Sequential Logic

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Figure 5.1
Block diagram of sequential circuit.

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Figure 5.2
Synchronous clocked sequential circuit.

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Figure 5.3
SR latch with NOR gates.

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Figure 5.4
SR latch with NAND gates.

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Figure 5.5
SR latch with control input.

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Figure 5.6
D latch.

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Figure 5.7
Graphic symbols for latches.

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Figure 5.8
Clock response in latch and flip-flop.

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Figure 5.9
Master–slave D flip-flop.

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Figure 5.10
D-type positive-edge-triggered flip-flop.

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Figure 5.11
Graphic symbol for edge-triggered D flip-flop.

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Figure 5.12
JK flip-flop.

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Figure 5.13
T flip-flop.

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Table 5.1
Flip-Flop Characteristic Tables.

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Figure 5.14
D flip-flop with asynchronous reset.

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Figure 5.15
Example of sequential circuit.

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Table 5.2
State Table for the Circuit of Fig. 5.15.

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Table 5.3
Second Form of the State Table.

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Figure 5.16
State diagram of the circuit of Fig. 5.15.

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Figure 5.17
Sequential circuit with D flip-flop.

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Figure 5.18
Sequential circuit with JK flip-flop.

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Table 5.4
State Table for Sequential Circuit with JK Flip-Flops.

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Figure 5.19
State diagram of the circuit of Fig. 5.18.

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Figure 5.20
Sequential circuit with T flip-flops (Binary Counter).

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Table 5.5
State Table for Sequential Circuit with T Flip-Flops.

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Figure 5.21
Block diagrams of Mealy and Moore state machines.

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Figure 5.22
Simulation output of Mealy_Zero_Detector.

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Figure 5.23
Simulation output of HDL Example 5.6.

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Figure 5.24
Simulation output of HDL Example 5.7.

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Figure 5.25
State diagram.

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Table 5.6
State Table.

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Table 5.7
Reducing the State Table.

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Figure 5.26
Reduced State diagram.

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Table 5.8
Reduced the State Table.

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Table 5.9
Three Possible Binary State Assignments.

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Table 5.10
Reduced State Table with Binary Assignment 1.

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Figure 5.27
State diagram for sequence detector.

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Table 5.11
State Table for Sequence Detector.

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Figure 5.28
K-Maps for sequence detector.

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Figure 5.29
Logic diagram of a Moore-type sequence detector.

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Table 5.12
Flip-Flop Excitation Tables.

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Table 5.13
State Table and JK Flip-Flop Inputs.

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Figure 5.30
Maps for J and K input equations.

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Figure 5.31
Logic diagram for sequential circuit with JK flip-flops.

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Figure 5.32
State diagram of three-bit binary counter.

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Table 5.14
State Table for Three-Bit Counter.

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Figure 5.33
Maps for three-bit binary counter.

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Figure 5.34
Logic diagram of three-bit binary counter.

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Figure P5.7

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Figure P5.8

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Problem 5.12

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Figure P5.19

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Figure P5.32
Waveforms for Problem 5.32.

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Figure P5.48

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Figure P5.49

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