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Lab 4 VXL

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25 views13 pages

Lab 4 VXL

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dai29b13088
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Lab 4: Introduction to

hardware description
language (cont)
Assignments
Continous assignment:

- Continuous assignments continuously monitor the RHS (right – hand side) and update the LHS (left –
hand side) immediately when the RHS change, does not introduce any timing delays.
- Multiple continous assignment executes concurrently, order of statements is not important.
- Used outside always statement to design simple combinational circuit.
- Syntax: assign LHS = RHS;

Blocking assignment:

- Cause the RHS expression to be evaluated immediately, and the LHS variable is updated before moving
to the next statement.
- Multiple blocking assignments are executed sequentially in the order they appear in the code, order of
statements is important.
- Used inside always statement to design combinational circuit.
- Syntax: LHS = RHS;

Non – blocking assignment:


- Updating for the variables on the LHS occur at the end of current time step, typically on a clock edge.
- Multiple non-blocking assignments executes concurrently, order of statements is not important.
- Used inside always statement to design more complex sequential circuit.
- Syntax: LHS <= RHS;
Compare between types of
assignments Continous Blocking Non-blocking
assignment assignment assignment
Update LHS to RHS Immediately Immediately At the end of
current time step,
typically on a clock
edge
Order of execution statements Concurrently In order Concurrently

Using to design Simple Combinational Sequential circuit


combinational circuit
circuit
Inside or outside Outside Inside Inside
always

Syntax assign a = b a=b a <= b


Always statement
Syntax:
always @(sensitivity list)
statement;
- Statements in always statement is executed only when the event specified in sensitivity list
occurs.

- always statement can be used to design flip-flop, latches or combinational circuit depend on
the sensitivity list and statement.

- Types of always statement:

+ always @(sensitivity list) can be used to design sequential or combinational circuit based
on sensitivity list
Ex: To design full adder: always@(a, b, cin)
To design D flip-flop: always@(posedge clk)
+ always_comb: is dedicated for designing combinational circuit; reevaluates the statements
inside always_comb any time the signal on RHS of statement changes.
+ always_latch is dedicated for design latch
+ always_ff is dedicated for design flip flop
Example on fulladder
Example: design a fulladder using always_comb statement

Using always_comb and blocking Using continuous assignment


assignment
module fulladder(input logic A, B, Cin, module full_adder(input logic A,B,Cin,
output logic S, Cout); output logic S, Cout);
logic P, G;
always_comb
begin logic P, G;
P = A ^ B; // blocking
G = A & B; // blocking assign P = A ^ B;
S = P ^ Cin; // blocking assign G = A & B;
Cout = G | (P & Cin); // blocking assign S = P ^ Cin;
end assign Cout = G | (P & Cin);
endmodule
endmodule
Packed array and unpacked array
Feature Packed array Unpacked array

Size/dimension to the left of variable name Size/dimension to the right of variable name
Declaration Ex: logic [3:0] data_bus; // 4 bits packed Ex: logic flag[3:0]; // 4 independent 1-bit logic
together variables
Storage Contiguous block of bits (compact in memory) Independent elements (not contiguous in memory)

Usage Represents multi-bit data like vectors, buses Represents independent variables (like arrays)

Bitwise Supported (since elements are bits) Not directly supported (need to access each element
Operations individually)

Arithmetic Supported (treats entire array as a number) Not directly supported for the entire array
Operations
Example:
// Packed Array: Represents a 4-bit bus or vector
logic [3:0] data_bus; // 4 bits packed together
module inverter(input logic [3:0] a, output logic [3:0] b);
// Unpacked Array: Array of independent variables
logic flag[3:0]; // 4 independent 1-bit logic variables
SystemVerilog numbers
- The format for declaring constants is N'Bvalue, where N is the
size in bits, B is a letter indicating the base, and value gives the
value.

Example, 9'h25 indicates a 9-bit number with avalue of


25(base 16) = 37(base 10) = 0001001012 (base 2).

- SystemVerilog supports 'b for binary, 'o for octal, 'd for decimal,
and ‘h for hexadecimal. If the base is omitted, it defaults
to decimal.
If-else statement
The syntax for an if-else statement in SystemVerilog is very similar to other programming languages
like C or Verilog. It is used to execute different blocks of code based on a conditional expression.

Syntax:
if (condition) begin
// Code to execute if condition is true
end else begin
// Code to execute if condition is false
end

Note: In SystemVerilog, if-else statement must appear inside always statement.


Case statement
Syntax:
case (expression)
value1: begin
// Code block to execute when expression == value1
//
end
value2: begin
// Code block to execute when expression == value2
//
end
// More value cases can be added here

default:
begin
// Code block to execute when expression doesn't match any value
// ...
end
endcase

Note: In SystemVerilog, case statement must appear inside always statement.


Exercise 1:
Design an 2-4 decoder using in SystemVerilog, simulate on ModelSim and test operations of
design in STEP MAX10 board.
Hint: using always_comb statement, blocking assignment and if-else or case structure

Example: module decoder2_4 (input logic [1:0] A,


output logic
[3:0] B);
Exercise 1:
Design an 2-4 decoder using in SystemVerilog, simulate on ModelSim and test operations of
design in STEP MAX10 board.
Hint: using always_comb statement, blocking assignment and if-else or case structure

Case statement If-else statement


Exercise 2:
Design an ALU using in SystemVerilog, simulate on ModelSim and test operations of design in
STEP MAX10 board.
Hint: using always_comb statement, blocking assignment and case structure

Opcode Operation
000 Add
001 Substract
010 And
011 Or
100 Xor
101 Equal

Example: module ALU(input logic A, B,


input logic [2:0] opcode,
output logic out);
Exercise 3:
Design a seven segment decoder using always_comb statement and case structure in
SystemVerilog, simulate on ModelSim and test operations of design in STEP MAX-10 board.
Hint: using always_comb statement and case structure

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