Seqencial Logic

Sequent Logi
ial Engr. Amirc

Habib Lectu
rer
Department of Software
Engineering
University of
Malakand
Digital Logic and Computer
Sequential
Logic
 Combinational circuits with memory
elements
called logic

sequential
diagra of .th sequenti logi is,
Block m e al c
2
Sequential
Logic
 Sequential circuit consists of
combinational logic
circuit to which memory
 elements are connected to form
a feedback path.

Memory elements are devices
capable of storing
binary information within them.

The binary information stored in the
memory elements at any given time
defines the state of the sequential
circuits. 3
Latches and Flop
Flip s
 A latch is a temporary storage device ha
that
two stable s
states.
 Its output can be changed by
applying
appropriate
inputs.
 A latch normally has two inputs, tw
and
output Q and o
s
 The Q’.is
Latch to be in Logi Hig when
said
 Q=1 and c h ,
Q’=0
 And vice
versa.
4
Flip
Flops
 A Latch is memory element which is
able to the information stored
retain
in it.flop circuit can be constructed
 Flip
from
NAND twoor NOR
Gates.
 The cross coupled connection
constitute
feedbac a
k.
 Such type circuits also called
ofcoupled RS are direct
flip flop SR latch.
or
5
Basic Flip Flop
Circuit
 The figur describe th circui as follow
e s e t ,
6
Basic Flip Flop
Circuit
 To analyze the operation of the
circuits on slide,
previous
 We know that the output of the NOR gate is 0
if any input is one, and vice versa.
 Starting for the draw tak all the
run
 an Reset= the e possibilities,
an Q’=
Set=1 d 0 n Q= d 0 Memor
 an Reset= the 1 an Q’= y
Set=0 d 0 n Q= d 0
 Memor
an Reset= the 1 an Q’= y
Set=0 Q= d 1
d 1 n
 (Indeterminate
an Reset= the 0 an Q’=
state)
Set=0

d 0 n Q= d 1 7
Fli Flo wit NAN Gate
p p h D s
For S=1, R=1, Q=0, Q’=1 after S=1, R=0 

Memory
For S=1, R=1, Q=1, Q’=0 after S=0, R=1 
Memory
8
RS-Flip
Flop
 The operation of the basic flip flop
can be
modified by providing an additional
control
input that determines when the state
of the
 An circuit
RS flip flop is to be
with a changed.
pulse(CP) is
clock shown.
circui an tw
 It consists of
additional basic flip t
NAND d o
flop
gates.
 CP acts as an enable input
signal .
9
RS- Flo
Flip
Q S R
p
Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 Invalid
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 invalid
10
D-Flip
Flop
 One way to eliminate the undesirable
condition
of the indeterminate state in the flop
to RS flip is
to ensure that inputs S and R are Equa
 never
It has only two inputs D and CP. l
1 at the same time.
 The D input directly goes to the S and
input complement is applied to R its
 input.
As long as the pulse input is at 0, the
outputs of
the gates 3 and 4 are at the one level
and the circuit cannot change state
regardless of the
D-Flip
Flop
 If D=1,
 Q output goes to 1, placing circuit the
the in set
state.
 If D=0,
 Q goe to 0, an circui switche to th clea
Output s d t s e r
state
.
12
D- Flo
Flip p
13
JK-Flip
Flop
 A JK flip flop is a refinement of the RS flip
flop
to over come the indeterminate
states.
 Input J and K behave like inputs S and Se
R and
to Clear the flip t
 Jflop.
for Set and K for Reset.
 A JK flip flop is constructed with two
cross
coupled NOR gates and two AND
gates. Q is ANDed with K and CP
 Output
inputs if Q
so that
 was the FF is cleared during a CP
previously
only
1.
14
JK-Flip
 Flop
Output Q’ is ANDed with J and CP inputs so
that
FF is se wit a CP onl whe Q’ wa previousl
1. t h y n s y
Q J K Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Characteristic
Table
15
JK-Flip Flo
p
16
T-Flip
Flop
 It’s a single version of JK flip flop.
input comes from the ability of
 The
FF todestination
“toggle”, the complement its state.
T or
 The table and equation show
characteristic that that is, the next
when T=0, Q(t+1)=Q,
state is
the same as the present state and no
change
 When occurs.
T=1, then Q(t+1)=Q’ and the
state
the of
FF is
complemented.
17
T-Flip Flo
p
18
Master Slave Flip
 A Master Slave FF is Flop
constructed from
two
separate
FF. circuit serves as a
 One and other as
master
slave, and the overall is a
calle to as a
circuit
Mast Slav Fli Flop d
er e p .
19
20

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Sequent Logi

ial Engr. Amirc

For S=1, R=1, Q=0, Q’=1 after S=1, R=0 

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