Combinational

Logic
En Amir
gr. Habib
Lecturer
UOM
Pakistan
Department of Software
Engineering

Digital Logic and Computer

Department of Computer Science 2
 Combinational
logic
 A combinational circuit consists of logic gates
whose
outputs at any time are determined directly
from the
present combination of inputs without regard
to
previous outputs.
 A combinational circuit performs a specific
information
processing operation fully specified logically by
a set of
Boolean functions.
 A Combinational circuit consists of input
variables, logic
gates, and output
variables.

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 Combinational
 logic
The logics gate accept signals from the
inputs and signals to the
generate
outputs.
 This process transforms binary information
from theinput data to the required output
given
data.
 Combination logi
 Design Procedures al c
 Starts from the verbal outline of the an
problem ends in a logic circuit d
diagram.
 The procedure involves the following
step,
 The problem is stated.

 Input and required output variables

are
determined.
outpu
 Assigned the variables letter symbols.
t
 Make the truth table.

 The simplified Boolean functions for

each 5
 Combinational
logic

Adders
 Adders are important in computers and also in
other
types of digital systems in which numerical
data are processed.
 An understanding of the basic adder operation
is
fundamental to the study of digital systems.
 The most basic operation is no doubt is the
addition of two binary digits.
 The Half
Adder
Half
Adder
 The circuit that performs the
combinational additions
of two bit is Half adder.
called
 One that the addition of three bits
performs including
two digits and previous carry is a full adder.
one
 Two half adders can be employed to form a full
adder.
 Combinational
logic
Half
Adder
 It has two inputs and two outputs.
 The input variables designates the augends
and addend bits; the output variables
produces the sum and carry.
 It is necessary to specify two output variables
because
the
 result
A and maytwo
B are consist of binary
inputs two binary digits.
whil C and
variables e S
used for carry and Sum to the
outputs.

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 Combinational
Half
logic
Adder
 The half-adder accepts two binary digits on its
inputs
and produces two binary digits on its outputs,
a sum bit and a carry bit.
 The truth table look like this,
A B Cout S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
 Combinational
Half logic
Adder
 A half-adder represente by th logi symb in
is Figur below d e c ol
e ,

Department of Computer 10
Science
 Half
Adder
 Half-Adder Logic
 Notice that the output Carry (Cout) is a 1 only
when
both A and B are 1s; Cout can be
therefore
as the AND of the input expressed
variables.
 C out =

 NowAB observe that the sum output (Σ) onl if

is a 1 y
the input
 The sum variables.
thereforeA be
and B, are as
notth
equal.
can expressed e
exclusive- of the input
OR variables.

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 Related
Example
 Half-Adder Logic
 The logic implementation required for the half
adder
function can be developed.
 The output carry is produced with an AND
gate with
A and B on the inputs.
 The sum output is generated with an
exclusive-OR
gate.
 Half
Adder
 Half-Adder Logic
diagram
Solution
s
 Full
Adder
Full
Adder
 The second category of adder is the full-adder.
 The full-adder accepts two input bits and an
input carry and generates a sum output
and an output carry.
 The basic difference between a full-adder
and a half-
adder is that the full-adder accepts an input
carry.
 Full
Adder
Logical symbol for full
adder is,
 Full Adde
Trut Tabl r
h e

Cin = input carry, sometime designated as CI

Cout = output carry sometimes designated as CO
Σ=sum
A and B = input variables (operands)
 Full
Adder
 Full Adder
Logic
 The full-adder must the two input bits and
add
inpu carry. the
t the half-adder know that the sum of
 you bits A and the
Fro B is the
variables, A xor B. exclusive-OR of those
m the input carry
 For two
to be added to the
(Cinpu
in )
bits. input
it must be exclusive-ORed with A xor B,
tyielding
the equation for the sum output of the full-
adder.
 Full Adde
r
 Map for Full Adde (For Su Function
r m )
yz
x

S= x’y’ + x’yz’ + xy’z’ +

z xyz
 Full Adde
r
Fo Carr Simplifie Expressio
r y d n
yz
x

C= xy + xz +
yz
Implementati of Full Adde in SO
on r P

Logic
Diagram
 Implementation of Full
Adder
Implementation of a full adder with two half
adders
and an OR Gate
Adder
s
 Proble
m
 For each of the three full-adders in
Figure
below, determine the outputs for the
inputs
shown.
Solutio
n
Qui
z
 Parallel Binary
Adders
 Two or more full-adders are connected to
form
parallel binary
adders.
 a single full-adder is capable of adding two
1-bit
numbers and an input
carry.
 To add binary numbers with more than
one
youbit,
must use additional full-
adders.
 When one binary number is added to
another,
each column generates a sum bit and a
1 or 0
carry bit to the next column to the left.
 Parallel Binary
Adder
 To add two binary numbers, a full-adder is
required for
 each bit in the numbers.
 So for 2-bit numbers, two adders are needed.
 For 4-bit numbers, four adders are used; and
so on.
The carry output of each adder is connected

to the
 for the least significant position or the carry a
carry input of the next higher-order adder.
input of is
Notice thatcan
full-adder either a half-adder
be made can bebecause
0 (grounded) used
there
no carry input to the least significant bit
position.
Parallel Binary
Adder
 Parallel Binary
Adder
 In Figure the least significant bits (LSB)
oftwo
thenumbers are represented by A1 and B1.
 The next higher-order bits are
represented
A2 and B2 . by
 The three sum bits are Σ1,Σ2 and Σ3.
Notice that the output carry from the left-
most
full-adder becomes the most
significant bit
(MSB) in the sum, Σ3.
 Exampl
 Determine the sum generated by e
the
3-bit
parallel adder and show the intermediate
carries
when the binary numbers 101 and 011
are
being added.
 Four Bit Parallel
Adder
 A group of four bits is called a nibble.
 A basic 4-bit parallel adder is
implemented with
four full-adder stages as shown in
Figure .
Logical Symbol for 4 bit Parallel
Adder
 4 bit parallel
adder
 The input labeled Co is the input carry
toleast
the significant bit
adder.
 C4 in the case of four bits, is the output carry of

the most significant bit adder; and Σ1

(LSB)
through
 The Σ4parallel
4-bit (MSB) are the sum
adder canoutputs.
be
expanded
handle the to addition of two 8-bit
numbers by
using two 4-bit adders.
 8 Bit
Adder

Cascading of two 4-bit adders to form an 8-bit

adder
 Subtracto
rs
 Subtraction of two binary
number is
accomplished by taking the complement
of the
subtrahend
 Logically andbe
it can adding
done it to the direct
through
minuend.
method.
 In this method
subtracted fromeach bit of the subtrahend
its corresponding
is minuend
significantbit form a difference bit.
tothe
 If bit is smaller then a 1
minuend
taken from borrow is
the next higher pair of the bits.
 Subtracto
rs
 Half Subtractor
 It subtract two bits and produces their
 It difference.
also has an output to specify if has
a1
borrowed. been
 x and y are minuend and veriable.
subtrahend magnitu of
 For subtraction we check the de
relative the x and y.
 If
 If x>=y thenit no
x<y then issue.
is necessary to take a borrow
from the
next higher stage.
 Hal subtract
f or
 Truth tabl of hal subtract is,
e f or
X Y B D
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

D=x’ y + x
y’
B=x’ y
 Proble
m
Draw a circuit diagram against Difference
D Borrow
and
B.
 Full
Subtractor
 It performs a subtraction between two
bits,
taking in to account that a 1 may have
been borrowed by a lower significant
stage.
 It has three inputs and two outputs.
 Three inputs x, y and z shows the
minuend,
subtrahend and previous borrow
respectively.
 B and D represents the output borrow
and
 Full
Subtractor
Truth table is as
under,
 Full
Subtractor
 The function against B and D
are,
 Code
conversion
 Some times the output of the one system
asinput
the to
another.
 If both the system uses different coding
system,
then code convertor is needed between
them.a code convertor is a circuit that
 Thus
makes
the two system
compatible.
 To convert from binary code A
to B,Input lines supply the bit combination of by
elements
Code A and the output lines must
generate the corresponding bit
combination for code B.
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 Code conversion BC to Exces 3 is
from
illustrate below D s
d ,

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Output Simplificati
s on

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Circui Diagra
t m

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Binar to Gra cod
y y e

50
Gra to Binar
y y

51
 Q?
Related Problem
How many exclusive- gate ar require to conver 8-
binar
OR to Gray s e d t bit
y ?

52
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