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03 Combinational Logic Design

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25 views27 pages

03 Combinational Logic Design

Uploaded by

mukesh.c
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DIGITAL ELECTRONICS

AND
MICROPROCESSORS
Combinational logic
design

By Ashok Ranade
Steps
 From the problem definition obtain the
truth table
 From the truth table obtain the
expression for the output
 Minimize the expression
Addition of two binary
numbers
A3 A2 A1 A0
B3 B2 B1 B0
S3 S2 S1 S0

1 1 0 1
0 1 0 1
1 0 0 1 0

13 Least significant bits are


5 added with two bit addition
18 circuit(Half adder)
Others need three bit
Design of half adder
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Sum = A’B + AB’


Carry = AB
No more simplification
possible
Problem
 A logic circuit has two inputs and one
output
 The output is 1 when the decimal
equivalent of the inputs in 2 and 3.
Otherwise
A Bit is 0 Y Y = AB’ +
0 0 0 AB
0 1 0 = A(B+B’)
=A
1 0 1
1 1 1
Karnaugh map
 This is an alternative method of writing
truth table
 Simplifies the minimization of the
expression for the output
Two variable Karnaugh map

Sum Output for half


adder
A 0 1
B
0 0 1
1 1 0

Note that input values are


written outside the map
and the output values are
written inside the map
For the problem

Output Y
A 0 1
B
0 0 1
1 0 1

Common values are


retained. For both 1s in
the output A is 1. But not
B. So B is eliminated and
Y=A
Full adder
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
3 Variable K map
Full adder carry

AB0 0 1 1
C
0 00 10 11 00
1 0 1 1 1

Carry = BC + AB + AC
Full adder Sum

AB
C 0 0 1 1
0 0 11 10 01
1 1 0 1 0

Sum = A’B’C + A’BC’ + ABC


+ AB’C’
A B C D a BCD to 7 segment
0 0 0 0 1 decoder
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X
For segment a

AB0 0 1 1
CD
00 10 10 1X 01
01 0 1 X 1
1 1 1 X X
1
1 1 1 X X
0
For segment a

AB0 0 1 1
CD
00 10 10 1X 01
01 0 1 X 1
1 1 1 X X
1
1 1 1 X X
0
C
For segment a

AB0 0 1 1
CD
00 10 10 1X 01
01 0 1 X 1
1 1 1 X X
1
1 1 1 X X
0
A
For segment a

AB0 0 1 1
CD
00 10 10 1X 01
01 0 1 X 1
1 1 1 X X
1
1 1 1 X X
0
BD
For segment a

AB0 0 1 1
CD
00 10 10 1X 01
01 0 1 X 1
1 1 1 X X
1
1 1 1 X X
0
B’D’
For segment a

AB0 0 1 1
CD
00 10 10 1X 01
01 0 1 X 1
1 1 1 X X
1
1 1 1 X X
0
Final expression
a = C + A + BD + B’ D’
Ca-Cc displays
Common anode and common cathode
displays
BCD to seven segment
decoder

Resistors are connected in series


with a, b, c etc to limit the current
through the LEDs
Truth table
Circuit
Simulation
Arduino implementation
Program
Simulation

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