19ECE349-RISC Processor

Design using HDL

Learning and Course Objectives
• Learning Objectives:

• LO1: To understand principles of processor architectures

• LO2: To familiarize with RISC design principles
• LO3: To design a pipelined processor using Verilog HDL
• Course Outcomes:

• CO1: Able to understand the concepts of pipelined computer architecture

• CO2: Able to design circuits using Verilog and understand concept of timing analysis

• CO3: Able to understand and design a MIPS based processor

• CO4: Able to implement a pipelined architecture of MIPS

• CO5: Able to understand memory hierarchy and design of cache memories

 Syllabus

• Unit I:

• Fundamental techniques of computer design – RISC and CISC architectures - computer arithmetic, - comparison
of RISC and CISC architectures - Introduction to superscalar and super pipelined architectures - Verilog
Introduction and review of basic designs using Verilog - Static timing analysis – Introduction - setup and hold
time constraints - processor timing issues - design examples.

• Unit II:

• MIPS Processor- Introduction to MIPS features and MIPS instruction set, logical design of MIPS datapath -
control unit and instruction decode - Design of single cycle - multi-cycle and pipelined architectures of MIPS -
Hazards- data and control hazards - Verilog designs of single cycle and multi-cycle MIPS processor.

• Unit III:

• Verilog design of pipelined MIPS processor - Introduction to memory hierarchy cache memory fundamentals -
memory systems for superscalar processors.
Textbook(s) and References:
Textbook(s):

• 1.Patterson, David A., and John L. Hennessy, “Computer Organization and Design: The Hardware Software
Interface”, Morgan kaufmann, First edition 2005.
• 2. Sarah L Harris, David Money Harris “, Digital Design and Computer Architecture RISC-V Edition
• 2. Palnitkar, Samir. “Verilog HDL: a guide to digital design and synthesis”, Edition 1, Prentice Hall
Professional, 2003.
Reference(s)
• 1.Hamacher, V. Carl, et al. “Computer organization”, Fifth edition. New York et al. McGraw-Hill, 1984.

• 2.Dandamudi, Sivarama P, “Guide to RISC processors: for programmers and engineers”, First edition, Springer
Science & Business Media, 2005.
Verilog HDL
Hardware description languages

• Verilog HDL
• VHDL

• Digital circuits could be described at a register transfer level (RTL) by

use of an HDL.
• The details of gates and their interconnections to implement the
circuit were automatically extracted by logic synthesis tools from the
RTL description
logic synthesis
• Thus, logic synthesis pushed the HDLs into the forefront of digital
design. Designers no longer had to manually place gates to build
digital circuits. They could describe complex circuits at an abstract
level in terms of functionality and data flow by designing those
circuits in HDLs.
• Logic synthesis tools would implement the specified functionality in
terms of gates and gate interconnections.
1.3 Typical Design Flow
• Unshaded blocks- level of
design representation
• shaded blocks - processes in
the design flow.
1.5 Popularity of Verilog HDL
 Popularity of Verilog HDL

• Verilog HDL is a general-purpose hardware description language that

is easy to learn and easy to use.
• It is similar in syntax to the C programming language.
• Designers with C programming experience will find it easy to learn
Verilog HDL.
• Verilog HDL allows different levels of abstraction to be mixed in the
same model.
• Thus, a designer can define a hardware model in terms of switches,
gates, RTL, or behavioural code.
Popularity of Verilog HDL
• Also, a designer needs to learn only one language for stimulus and
hierarchical design.
• Most popular logic synthesis tools support Verilog HDL. This makes it
the language of choice for designers.
Popularity of Verilog HDL
• All fabrication vendors provide Verilog HDL libraries for post logic
synthesis simulation. Thus, designing a chip in Verilog HDL allows the
widest choice of vendors.
• The Programming Language Interface (PLI) is a powerful feature that
allows the user to write custom C code to interact with the internal
data structures of Verilog.
Chapter 2. Hierarchical
Modeling
Concepts
2.1 Design Methodologies
(Hierarchical Modeling
Concepts)
Design Methodologies
• There are two basic types of digital design methodologies:
• A top-down design methodology.
• bottom-up design methodology.
 A top-down design methodology

• In a top-down design methodology, we define the top-level block and identify the
sub-blocks necessary to build the top-level block.
• We further subdivide the sub-blocks until we come to leaf cells, which are the
cells that cannot further be divided.
A top-down design methodology
 bottom-up design methodology.

• In a bottom-up design methodology, we first identify the building

blocks that are available to us.
• We build bigger cells, using these building blocks.
• These cells are then used for higher-level blocks until we build the
top-level block in the design.
bottom-up design methodology.
 Hierarchical Modeling Concepts
• Typically, a combination of top-down and bottom-up flows is used.
• Design architects define the specifications of the top-level block.
• Logic designers decide how the design should be structured by breaking up the
functionality into blocks and sub-blocks.
• At the same time, circuit designers are designing optimized circuits for leaf-level cells.
• They build higher-level cells by using these leaf cells.
• The flow meets at an intermediate point where the switch-level circuit designers have
created a library of leaf cells by using switches, and the logic level designers have
designed from top-down until all modules are defined in terms of leaf cells.
4-bit Ripple Carry Counter
T-flipflop
Design Hierarchy
D Latch
Negative edge triggered D flip-flop
JK flip-flop using D flip-flop
T flip-flop using D flip-flop
2.2 4-bit Ripple Carry Counter
2.2 4-bit Ripple Carry Counter
• To illustrate these hierarchical modeling concepts, let us consider the
design of a negative edge-triggered 4-bit ripple carry counter
Design Hierarchy
D-Flip Flop
module D-FF(q, d, clk, reset) ;
D q
output q;
input d, clk, reset; clk
reg q;
always @(posedge reset or negedge clk)
if (reset) reset
q = 1'b0;
else
q = d;
endmodule
T-flipflop
T-Flip Flop
module T-FF(q, clk, reset) ;
output q;
input clk, reset;
wire d; module D-FF(q, d, clk, reset) ;
output q;
D-FF dff0 (q, d, clk, reset) ; input d, clk, reset;
reg q;
not nl(d, q); always @(posedge reset or negedge clk)
if (reset)
endmodule q = 1'bO;
else
q = d;
endmodule
4-bit Ripple Carry Counter
4-bit Ripple Carry Counter
module ripple-carry-counter(q, clk, reset);
output [3:0] q;
input clk, reset;

module T-FF(q, clk, reset) ;

output q;
input clk, reset;
endmodule wire d;
D-FF dff0 (q, d, clk, reset) ;
not nl(d, q);
endmodule
4-bit Ripple Carry Counter
module ripple-carry-counter(q, clk,
reset);
output [3:0] q;
input clk, reset;
T-FF tffO(q[0],clk,reset);
T-FF tff1(q[1] ,q[0], reset); module T-FF(q, clk, reset) ;
output q;
T-FF tff2 (q[2] ,q[1], reset) ; input clk, reset;
wire d;
T-FF tff3(q[3] ,q[2], reset) ; D-FF dff0 (q, d, clk, reset) ;
not nl(d, q);
endmodule endmodule
2.3 Modules
Modules
module <module_name> T-flipflop could be defined as a
(<module_terminal_list>); module as follows:
.. module T_FF (q, clock, reset);
<module internals> .
... .
... <functionality of T-flipflop>
endmodule .
.
endmodule
Verilog Different level of abstraction or Modeling

• Gate level
• Dataflow level
• Behavioral or algorithmic level
• Switch level
Gate level Modeling

• The module is implemented in terms of logic gates and interconnections

between these gates.
• Design at this level is similar to describing a design in terms of a gate-level
logic diagram.
• Not practical for large examples
 and gate design using Gate level modeling

module andgate(c,a,b); Port List

// Port declarations from the I/O diagram
input a,b; Primary I/P
output c; Primary o/p

• // Specify the function of a design

and a1(c,a,b);
endmodule
 l-bit Full Adder design using gate-level modeling

Primary I/P
Internal Nets
Primary o/p

module fulladd(sum, c_out, a, b, c_in);

l-bit Full Adder design using gate-level modeling

// Define a 1-bit full adder

module fulladd(sum, c_out, a, b, c_in);
// Port declarations from the I/O diagram
output sum, c_out;
input a, b, c_in;
// Internal nets
wire s1, s2, c1;
// Specify the function of a design
xor x1(s1, a, b);
and a1(c1, a, b);
xor x1(sum, s1, c_in);
and a1(s2, s1, c_in);
or r1(c_out, s2, c1);
endmodule
4-to-1 Multiplexer design using gate level modeling
Logic Diagram for Multiplexer

module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

Logic Diagram for Multiplexer

module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

output out;
input i0, i1, i2, i3;
input s1, s0;
wire s1n, s0n;
wire y0, y1, y2, y3;
not n1(s1n, s1);
not n2(s0n, s0);
and a1(y0, i0, s1n, s0n);
and a2(y1, i1, s1n, s0);
and a3(y2, i2, s1, s0n);
and a4(y3, i3, s1, s0);
or r1(out, y0, y1, y2, y3);
endmodule
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
output out; // Port declarations from the I/O diagram
input i0, i1, i2, i3;
input s1, s0;
wire s1n, s0n; // internal nets
wire y0, y1, y2, y3; // internal nets
Verilog Description of Multiplexer
not n1(s1n, s1); // Functionality of the design
not n1(s0n, s0);
and a1(y0, i0, s1n, s0n);
and a2(y1, i1, s1n, s0);
and a3(y2, i2, s1, s0n);
and a4(y3, i3, s1, s0);
or r1(out, y0, y1, y2, y3);
endmodule
 Dataflow level modeling
• At this level the module is designed by specifying the data flow.
• The flow of data through components is specified based on
the idea of how data is processed.
• The designer is aware of how data flows between hardware registers
and how the data is processed in the design.
module fulladd4(sum, c_out, a, b, c_in);
// Port declarations from the I/O diagram
output sum;
output c_out;
Input a, b;
input c_in;
// Specify the function of a full adder
assign {c_out, sum} = a + b + c_in;
endmodule
2x1 mux design using data flow modeling
2x1 mux design using data flow modeling

module mux_2x1 ( f,io,i1,x);

output f;
input io, i1;
input x;
assign f = x ? i1 : Io;
endmodule
 4x1 mux design using data flow modeling
module mux_4x1 ( M,X0, X1,X2,X3,C1, C0);
output M;
input X0, X1, X2, X3, C1,C0;
assign M = C1 ? (C0 ? X2 : X3) : (C0 ? X1: X0);
endmodule
1-bit Full Adder, Using Dataflow modeling
module fulladder(sum, c_out, a, b, c_in);
// Port declarations from the I/O diagram
output sum;
output c_out;
Input a, b;
input c_in;
// Specify the function of a full adder
assign {c_out, sum} = a + b + c_in;
endmodule
4-bit Adder, Using Dataflow modeling
module adder4(sum, c_out, a, b, c_in);
output [3:0] sum;
output c_out;
input[3:0] a, b;
input c_in;
// Specify the function of a full adder
assign {c_out, sum} = a + b + c_in;
endmodule
 Behavioral or algorithmic level
• This is the highest level of abstraction provided by Verilog HDL.
• Design specified in terms of algorithm (functionality) without hardware details.
• A module can be implemented in terms of the desired design algorithm without concern for the
hardware implementation details.
• Designing at this level is very similar to C programming.
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;
reg out;
always @(s1 or s0 or i0 or i1 or i2 or i3)
case ({s1, s0}) //Switch based on concatenation of control
signals
2’b00 : out = i0;
2’b01 : out = i1;
2’b10 : out = i2;
2’d11 : out = i3;
default: $display("Invalid control signals");
endcase
endmodule
4-to-1 Multiplexer design using Behavioral modeling

module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;
reg out;
always @(s1 or s0 or i0 or i1 or i2 or i3)
case ({s1, s0}) //Switch based on concatenation of control signals
2'd0 : out = i0;
2'd1 : out = i1;
2'd2 : out = i2;
2'd3 : out = i3;
default: $display("Invalid control signals");
endcase
endmodule
4-bit Full Adder design using gate-level
modeling
l-bit Full Adder design using gate-level modeling
// Define a 1-bit full adder
module fulladd(sum, c_out, a, b, c_in);
output sum, c_out;
input a, b, c_in;
// Internal nets
wire s1, s2, c1;

xor (s1, a, b);

and (c1, a, b);
xor (sum, s1, c_in);
and (s2, s1, c_in);
or (c_out, s2, c1);
4-bit Full Adder design using gate-level modeling
 4-bit Ripple Carry Full
// Define a 4-bit full adder Adder
module fulladd4(sum, c_out, a, b, c_in);
output [3:0] sum;
output c_out;
input[3:0] a, b;
input c_in;
// Internal nets
wire c1, c2, c3;
fulladd fa0(sum[0], c1, a[0], b[0], c_in);
fulladd fa1(sum[1], c2, a[1], b[1], c1);
fulladd fa2(sum[2], c3, a[2], b[2], c2);
fulladd fa3(sum[3], c_out, a[3], b[3], c3);
endmodule
4-bit Full Adder design using gate-level modeling

module fulladd4(sum, c_out, a, b, c_in);

module fulladd(sum, c_out, a, b, c_in);
fulladd fa0(sum[0], c1, a[0], b[0], c_in);
2.5 Components of a Simulation
Components of a Simulation

• Once a design block is completed,

it must be tested. The
functionality of the design block
can be tested by applying stimulus
and checking results.
• We call such a block the
stimulus block. It is good
practice to keep the stimulus and
design blocks separate.
• The stimulus block is also
commonly called a test bench.
Stimulus Block
module andgate (c,a,b); module stimulus;
reg at;
input a,b; reg bt;
output c; wire ct;
// instantiate the design block
and a1(c,a,b);
andgate t1(ct, at, bt);
initial
endmodule begin
#5 at = 1'b0; bt=1’b0;
#10 at = 1'b0; bt=1’b1;
#5 at = 1'b1; bt=1’b0;
#5 at = 1'b1; bt=1’b1;
end
endmodule
Stimulus Block
module ripple-carry-counter(q, clk, reset) ;
output [3:0] q;
input clk, reset;

T-FF tffO(q[O] ,clk, reset)

T-FF tffl(q[l] ,q[O], reset
T-FF tff2 (q[2] ,q[l], reset
T-FF tff3 (q[3l ,q[2], reset

endmodule
Stimulus Block

module stimulus;
reg clk;
reg reset;
wire[3:0] q;
// instantiate the design block
ripple-carry-counter rl(q, clk, reset);
// Control the clk signal that drives the design block.Cycle time = 10ns
initial
clk = 1'b0; //set clk to 0
always
#5 clk = -clk; //toggle clk every 5 time units
Stimulus Block
// Control the reset signal that drives the design block

initial
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $finish; //terminate the simulation
end
// Monitor the outputs
initial
$monitor ($time, " Output q = %d" , q) ;
endmodule
initial
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $finish; //terminate the simulation
end
// Monitor the outputs
initial
$monitor ($time, " Output q = %d" , q) ;
endmodule
initial
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20
$finish; //terminate the simulation
end
// Monitor the outputs
initial
$monitor ($time, " Output q = %d" , q) ;
endmodule
l-bit Full Adder design using gate-level modeling

// Define a 1-bit full adder

module fulladd(sum, c_out, a, b, c_in);
// Port declarations from the I/O diagram
output sum, c_out;
input a, b, c_in;
// Internal nets
wire s1, s2, c1;
// Specify the function of a design
xor x1(s1, a, b);
and a1(c1, a, b);
xor x1(sum, s1, c_in);
and a1(s2, s1, c_in);
or r1(c_out, s2, c1);
endmodule
Testbench or Stimulus block for full adder

//Design block //Test bench or Stimulus block

// Define a 1-bit full adder module testfulladd;
module fulladd(sum, c_out, a, b, c_in); reg a, b, c_in;
// Port declarations from the I/O diagram wire sum, c_out;
output sum, c_out; // instantiate the design block
input a, b, c_in; fulladd f1(sum, c_out, a, b, c_in);
// Internal nets initial
wire s1, s2, c1; begin
// Specify the function of a design #5 a = 1'b0; b=1’b0; c_in=1’b0;
xor x1(s1, a, b); #10 a = 1'b0; b=1’b1; c_in=1’b1
and a1(c1, a, b); #5 at = 1'b1; bt=1’b0; c_in=1’b0
xor x1(sum, s1, c_in);
#5 at = 1'b1; bt=1’b1; c_in=1’b1
and a1(s2, s1, c_in);
end
or r1(c_out, s2, c1);
endmodule
endmodule
D-Flip Flop
module D-FF(q, d, clk, reset) ;
D q
output q;
input d, clk, reset; clk
reg q;
always @(posedge reset or negedge clk)
if (reset) reset
q = 1'b0;
else
q = d;
endmodule
Test Bench stimulus block for D-flip flop

• module D-FF(q, d, clk, reset) ; module stimulus;

• output q; reg clk, d;
• input d, clk, reset; reg reset;
• reg q; wireq;
• always @(posedge reset or negedge clk) // instantiate the design block
• if (reset) D-FF d1(q, d, clk, reset);
• q = 1'bO; // Control the clk signal that drives the design
block.Cycle time = 10ns
• else initial
• q = d; clk = 1'b0; //set clk to 0
• endmodule always
#10 clk = ~(clk); //toggle clk every 10 time units
 Test Bench stimulus block for D-flip flop

• module D-FF(q, d, clk, reset) ; // Control the reset signal that drives the design block
initial
• output q; begin
• input d, clk, reset; reset = 1'b1;
#15 reset = 1’b0;
• reg q;
#20 D=1’b1;
• always @(posedge reset or #180 reset = 1'b1;
negedge clk) #10 reset = 1’b0;
#10 D=1’b1;
• if (reset)
#20 $finish; //terminate the simulation
• q = 1'bO; end
• else // Monitor the outputs
initial
• q = d; $monitor ($time, " Output q = %d" , q) ;
• endmodule endmodule
Logic Diagram for Multiplexer- Gate level modeling

module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

output out;
input i0, i1, i2, i3;
input s1, s0;
wire s1n, s0n;
wire y0, y1, y2, y3;
not (s1n, s1);
not (s0n, s0);
and (y0, i0, s1n, s0n);
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);
or (out, y0, y1, y2, y3);
endmodule
Bitwise- (data flow modelling)
Logical
Conditional Operator- data flow modelling)

//model functionality of a 2-to-1 mux

assign out = control ? in1 : in0;
 4-to-1 Multiplexer (Logical operation)(data flow modelling)

module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

output out;
input i0, i1, i2, i3;
input s1, s0;
//Logic equation for out
assign out = (~s1 & ~s0 & i0)|
(~s1 & s0 & i1) |
(s1 & ~s0 & i2) |
(s1 & s0 & i3) ;
endmodule
Multiplexer, Using Conditional Operators
module multiplexer4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;
// Use nested conditional operator
assign out = s1 ? ( s0 ? i3 : i2) : (s0 ? i1 : i0) ;
endmodule
4-bit Adder, Using Dataflow Operators
module add4(sum, c_out, a, b, c_in);
output [3:0] sum;
output c_out;
input[3:0] a, b;
input c_in;
// Specify the function of a full adder
assign {c_out, sum} = a + b + c_in;
endmodule
Stimulus for 4-bit Ripple Carry Full Adder
module stimulus;
// Set up variables
reg [3:0] A, B;
reg C_IN;
wire [3:0] SUM;
wire C_OUT;
fulladd4 FA1_4(SUM, C_OUT, A, B, C_IN);
Initial
begin
A = 4'd0; B = 4'd0; C_IN = 1'b0;
#5 A = 4'd3; B = 4'd4;
#5 A = 4'd2; B = 4'd5;
#5 A = 4'd9; B = 4'd9;
#5 A = 4'd10; B = 4'd15;
#5 A = 4'd10; B = 4'd5; C_IN = 1'b1;
end
initial
begin
$monitor($time," A= %b, B=%b, C_IN= %b, --- C_OUT= %b, SUM= %b ",A, B, C_IN, C_OUT, SUM);
end
endmodule
 The output of the simulation is shown below.

0 A= 0000, B=0000, C_IN= 0, --- C_OUT= 0, SUM= 0000 A = 4'd0; B = 4'd0; C_IN = 1'b0;
5 A= 0011, B=0100, C_IN= 0, --- C_OUT= 0, SUM= 0111 #5 A = 4'd3; B = 4'd4;
10 A= 0010, B=0101, C_IN= 0, --- C_OUT= 0, SUM= 0111 #5 A = 4'd2; B = 4'd5;
15 A= 1001, B=1001, C_IN= 0, --- C_OUT= 1, SUM= 0010 #5 A = 4'd9; B = 4'd9;
20 A= 1010, B=1111, C_IN= 0, --- C_OUT= 1, SUM= 1001
#5 A = 4'd10; B = 4'd15;
25 A= 1010, B=0101, C_IN= 1 --- C_OUT= 1, SUM= 0000
#5 A = 4'd10; B = 4'd5; C_IN = 1'b1;
Behavioral 4-bit Counter Description
//4-bit Binary counter
module counter(Q , clock, clear);
output [3:0] Q;
input clock, clear;
reg [3:0] Q;
always @( posedge clear or negedge clock)
begin
if (clear)
Q <= 4'd0; //Nonblocking assignments are recommended
//for creating sequential logic such as flipflops
else
Q <= Q + 1;// Modulo 16 is not necessary because Q is a
// 4-bit value and wraps around.
end
endmodule
3. Basic Concepts
 Basic Concepts
module stimulus;
• Verilog Conventions reg clk;
• The basic conventions used by reg reset;
Verilog HDL are similar to those in wire[3:0] q;
the C programming language. // instantiate the design block
• Verilog contains a stream of tokens. ripple-carry-counter rl(q, clk, reset);
• Tokens can be comments, numbers, // Control the clk signal that drives the design
block.Cycle time = 10ns
strings, identifiers, and keywords.
initial
• Verilog HDL is a case-sensitive clk = 1'b0; //set clk to 0
language. All keywords are in always
lowercase. #5 clk = -clk; //toggle clk every 5 time units
 Whitespace

• Blank spaces (\b) , tabs (\t) and newlines (\n)

• Whitespace is ignored by Verilog except when it separates tokens.
Whitespace is not ignored in strings.
Comments
• Comments can be inserted in the code for a = b && c; // This is a one-line comment
readability and documentation. There are
two ways to write comments.
• A one-line comment starts with "//". /* This is a multiple line comment */
Verilog skips from that point to the end
of line. /* This is /* an illegal */ comment */
• A multiple-line comment starts with "/*“ /* This is //a legal comment */
and ends with "*/".
• Multiple-line comments cannot be
nested.
• However, one-line comments can be
embedded in multiple-line comments.
 Operators
a = ~b; // ~ is a unary operator. b is the operand
• Operators are of three types, unary,
binary, and ternary.
• Unary operators precede the operand. a = b && c; // && is a binary operator. b and c are operands
• Binary operators appear between two
operands. a = b ? c : d; // ?: is a ternary operator. b, c and d are operands
• Ternary operators have two separate
operators that separate three operands.
 Number Specification
• There are two types of number specification in Verilog:
sized and unsized.
 Sized numbers
• Sized numbers are represented as <size> 4'b1111 // This is a 4-bit
<base format> <number> binary number
• <size> is written only in decimal and
specifies the number of bits in the number. 12‘habc // This is a 12-bit
• Legal base formats are decimal ('d or 'D), hexadecimal number
hexadecimal ('h or 'H), binary ('b or 'B) and 16'd255 // This is a 16-bit
octal (‘o or ‘O)
decimal number.
• The number is specified as consecutive
digits from 0,1,2,3, 4,5, 6, 7, 8, 9, a, b, c, d,
e, f.
• Only a subset of these digits is legal for a
particular base. Uppercase letters are legal
for number specification.
 Unsized numbers
• Numbers that are specified without a 23456 // This is a 32-bit decimal number by
default
<base format> specification are
decimal numbers by default. 'hc3 // This is a 32-bit hexadecimal number
• Numbers that are written without a '021 // This is a 32-bit octal number
<size> specification have a default
number of bits that is simulator- and
machine-specific (must be at least 32).
 X or Z values
• Verilog has two symbols for 12'h13x // This is a 12-bit hex number; 4
unknown and high impedance least significant bits unknown
values 6'hx //This is a 6-bit hex number
• These values are very important
for modelling real circuits.
• An unknown value is denoted by
an X
• A high impedance value is
denoted by z.
X or Z values
• An x or z sets four bits for a number in the hexadecimal base,
three bits for a number in the octal base,
• and one bit for a number in the binary base.
Negative numbers
• Negative numbers can be specified by putting a minus sign
before the size for a constant number.
• Size constants are always positive.
• It is illegal to have a minus sign between <base format>
and <number>.

-8'd3 // 8-bit negative number stored as 2's complement of 3

4'd-2 // Illegal specification
Underscore characters and question marks
• An underscore character "-" is allowed anywhere in a number except
the first character.
• Underscore characters are allowed only to improve readability of
numbers and are ignored by Verilog
12'b1111_0000_1010// Use of underline characters for readability
 Strings
• A string is a sequence of characters that are enclosed by double
quotes.

"Hello Verilog World" // is a string

Identifiers and Keywords
reg [3:0] a; // ‘reg’ is a keyword; ‘a’ is an identifier
reg value; // reg is a keyword; value is an identifier
input clk; // input is a keyword, clk is an identifier

• Keywords are special identifiers reserved to define the language

constructs.
• Keywords are in lowercase.
 Identifiers and Keywords

• Identifiers are names given to objects so that they can be

referenced in the design.
• Identifiers are made up of alphanumeric characters, the
underscore ( - ) and the dollar sign ( $ ) and are case sensitive.
• Identifiers start with an alphabetic character or an underscore.
They cannot start with a number or a $ sign
Escaped Identifiers
• Escaped identifiers begin with the backslash ( \ ) character
and end with whitespace (space, tab, or newline).

• All characters between backslash and whitespace are processed literally.

• Any printable ASCII character can be included in escaped identifiers
3.2 Data Types
Value Set
• Verilog supports four values and eight strengths to model
the functionality of real hardware.
four values
Strength levels
• In addition to logic values, strength levels are often used to
resolve conflicts between drivers of different strengths in digital
circuits.
Value levels o and 1 can have the strength levels
Nets
• Nets represent connections between hardware elements.
• Nets are declared primarily with the keyword wire.
• The default value of a net is z
wire a; // Declare net a
wire b,c; // Declare two wires b,c
wire d = 1’b0; // Net d is fixed to logic value 0 at declaration.
 Nets
• Note that net is not a keyword but represents a class of data types
such as wire,wand, wor, tri, triand, trior, trireg, etc.
• The wire declaration is used most frequently.
Registers
• Registers represent data storage elements. Registers retain
value until another value is placed onto them.
• Register data types are commonly declared by the keyword
reg. The default value for a reg data type is X
reg reset; // declare a variable reset that can hold its value
initial // this construct will be discussed later
begin
reset = 1'b1; //initialize reset to 1 to reset the digital circuit.
#l00 reset = l'bO; // after 100 time units reset is deasserted.
end
Vectors
• Nets or reg data types can be declared as vectors (multiple bit widths).
• If bit width is not specified, the default is scalar (1-bit).
Vectors
• wire a; // scalar net variable, default
• wire [7:0] bus; // 8-bit bus
• wire [31:0] busA,busB,busC; // 3 buses of 32-bit width.
• reg clock; // scalar register, default
• reg [0 : 40] virtual-addr; // vector register, virtual address 41 bits wide
• Vectors can be declared at [high# : low#] or [low# : high#], but the left
number in the squared brackets is always the most significant bit of the
vector.
Vector Part Select
• it is possible to address bits or parts of vectors. • wire a; // scalar net variable,
• busA[7] // bit 7 of vector bus A default
• bus[2:0] // Three least
significant bits of vector bus, • wire [7:0] bus; // 8-bit bus
• // using bus[0:2] is illegal • wire [31:0] busA,busB,busC; // 3
because the significant bit
should buses of 32-bit width.
• // always be on the left of a • reg clock; // scalar register,
range specification
• virtual-addr [0:1] //Two most
default
significant bits of vector • reg [0 : 40] virtual-addr; //
virtual-addr
vector register, virtual address
41 bits wide
 Variable Vector Part Select
• Another ability provided in Verilog HDL is to have variable part selects of a
vector. This allows part selects to be put in for loops to select various parts of
the vector.
• There are two special part-select operators:
[<starting_bit>+:width] - part-select increments from starting bit
Variable Vector Part Select
• reg [255:0] data1; //Little endian notation
• reg [0:255] data2; //Big endian notation
• reg [7:0] byte;
• //Using a variable part select, one can choose parts
• byte = data1[31-:8]; //starting bit = 31, width =8 => data[31:24]
• byte = data1[24+:8]; //starting bit = 24, width =8 => data[31:24]
• byte = data2[31-:8]; //starting bit = 31, width =8 => data[24:31]
• byte = data2[24+:8]; //starting bit = 24, width =8 => data[24:31]
Integer, Real, and Time Register Data Types
• Integer, real, and time register data types are supported in Verilog.
 Integer
• An integer is a general-purpose register data type used for manipulating
quantities.
• Integers are declared by the keyword integer.
• Although it is possible to use reg as a general-purpose variable, it is more
convenient to declare an integer variable for purposes such as counting.
• The default width for an integer is the host-machine word size, which is
implementation-specific but is at least 32 bits.
• Registers declared as data type reg store values as unsigned quantities,
• whereas integers store values as signed quantities.
Integer
• integer counter; // general purpose variable used as a counter.
initial
counter = -1; // A negative one is stored in the counter
 Real
• Real number constants and real register data types are declared with
the keyword real.
• They can be specified in decimal notation (e.g., 3.14) or in
scientific notation (e.g., 3e6, which is 3 X10^6 ).
• Real numbers cannot have a range declaration, and their default
value is 0.
• When a real value is assigned to an integer, the real number is
rounded off to the nearest integer.
 Real
real delta; // Define a real variable called delta
initial
begin
•
delta = 4e10; // delta is assigned in scientific
.

notation
delta = 2.13; // delta is assigned a value 2.13
end
integer i; // Define an integer i
initial
i = delta; // i gets the value 2 (rounded value of 2.13)
 Time
• Verilog simulation is done with respect to simulation time. A
special time register data type is used in Verilog to store
simulation time.
• A time variable is declared with the keyword time.
• The width for time register data types is implementation specific
but is at least 64 bits.
• The system function $time is invoked to get the current simulation
time.
Time
time save-sim-time; // Define a time variable save-sim-time
initial
save-sim-time = $time; // Save the current simulation time
Stimulus Block
// Control the reset signal that drives the design block
// reset is asserted from 0 to 20 and from 195 to 205.
initial
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $finish; //terminate the simulation
end
// Monitor the outputs
initial
$monitor ($time, " Output q = %d" , q) ;
endmodule
One dimensional Arrays wire [7:0] bus; // 8-bit bus
Two dimensional Arrays
 Vector Vs Arrays
Vector: Arrays:
• A vector is a single
• arrays are multiple elements
element that is n-bits
wide. that are 1-bit or n-bits wide.
Arrays
• Arrays are allowed in Verilog for net, reg, integer, time, real and vector
register data types.
• Multi-dimensional arrays can also be declared with any
number of dimensions.
integer count[0:7]; // An array of 8 count variables
reg bool[31:0]; // Array of 32 one-bit boolean register variables
time chk_point[1:100]; // Array of 100 time checkpoint variables
Arrays
wire [7:0] w_array2 [5:0]; // Declare an array of 8 bit vector wire
reg [4:0] port_id[0:7]; // Array of 8 port_ids; each
port_id is 5 bits wide

wire w_array1[7:0][5:0]; // Declare an array of

single bit wires
integer matrix[4:0][0:255]; // Two dimensional array of integers
reg [63:0] array_4d [15:0][7:0][7:0][255:0]; //Four dimensional array
 Assignments to elements of arrays
integer count[0:7]; count[5] = 0;
time chk_point[1:100]; chk_point[100] = 0;
reg [4:0] port_id[0:7];
port_id[3] = 0; //5 bits
--------------------
port_id = 0; //Illegal syntax
integer matrix[4:0][0:255];
matrix[1][0] = 33559;
Memories
• Memories are modeled in Verilog simply as a one-
dimensional array of registers.
• Each element of the array is known as an element or
word
• reg mem1bit[0:1023]; // Memory mem1bit with 1K
1-bit words
• reg [7:0] membyte[0:1023]; // Memory membyte
with 1K 8-bit words(bytes)
• membyte[511] // Fetches 1 byte word whose
address is 511.
Chapter 4. Modules and Ports
4.1 Modules
Components of a Verilog Module
 Components of a Verilog Module

• A module definition always

begins with the keyword
module.
• The module name, port list,
port declarations, and optional
parameters must come first in
a module definition.
• Port list and port declarations
are present only if the module
has any ports to interact with
the external environment.
Components of a Verilog Module

The five components within a module

are:
variable declarations,
dataflow statements,
instantiation of lower modules,
behavioral blocks,
and tasks or functions.
These components can be in any order
and at any place in the module
definition.
 Components of a Verilog Module

• The endmodule statement

must always come last in a
module definition.
• All components except module,
module name, and endmodule
are optional and can be mixed
and matched as per design
needs.
• Verilog allows multiple modules
to be defined in a single file.
• The modules can be defined in
any order in the file.
4.2 Ports
Ports
• Ports provide the interface by which a module can
communicate with its environment.
• For example, the input/output pins of an IC chip are its
ports. The environment can interact with the module
only through its ports.
List of Ports
• Input
• Output
• Inout
List of Ports
• A module definition contains an optional list of ports.
• If the module does not exchange any signals with the
environment, there are no ports in the list.
I/O Ports for Top and Full Adder
 I/O Ports for Top and Full Adder

• module fulladd4(sum, c_out, a, b, c_in); • the module Top is a top-level module.

//Module with a list of ports • The module fulladd4 is instantiated
below Top.
• module Top; // No list of ports, top-level • The module fulladd4 takes input on
module in simulation ports a, b, and c_in and produces an
output on ports sum and c_out.
• Thus, module fulladd4 performs an
addition for its environment
• The module Top is a top-level
module in the simulation and does
not need to pass signals to or receive
signals from the environment.
• Thus, it does not have a list of ports.
Port Declaration
• All ports in the list of ports must be declared in the
module.
Port Declaration
• Each port in the port list is defined as input, output, or inout, based on the
direction of the port signal.

module fulladd4(sum, c_out, a, b, c_in);

//Begin port declarations section
output[3:0] sum;
output c_cout;
input [3:0] a, b;
input c_in;
• //End port declarations section
• ...
• <module internals>
• ...
• endmodule
 Port Declaration
• Note that all port declarations are implicitly declared as wire
in Verilog.
• input or inout ports are normally declared as wires.
Port Declaration
• However, if output ports hold their value, they must be
declared as reg.
• For example, in the definition of DFF
module DFF(q, d, clk, reset);
output q;
reg q; // Output port q holds value; therefore it is declared as reg.
input d, clk, reset;
...
...
endmodule
Port Declaration
• Ports of the type input and inout cannot be declared as
reg
Port Declaration
• the module fulladd4 can be declared using an ANSI C style
module fulladd4(output reg [3:0] sum,
output reg c_out,
input [3:0] a, b, //wire by default
input c_in); //wire by default
...
<module internals>
...
endmodule
Reg data type rule
• Any output or any variable value is assigned inside the always or initial
block(Behavioral block)that must be assigned as a register by the key
word reg
module D-FF(q, d, clk, reset) ;
output q;
input d, clk, reset;
reg q;
always @(posedge reset or negedge clk)
if (reset)
q = 1'b0;
else
q = d;
endmodule
Port Connection Rules
• One can visualize a port as consisting of two units, one
unit that is internal to the module and another that is
external to the module.
• internal to the module- design
• external to the module –test bench
Port Connection Rules

Inputs
• Internally, input ports must always
be of the type net.
• Externally, the inputs can be
connected to a variable which is a
reg or a net.
Outputs
• Internally, outputs ports can be of
the type reg or net.
• Externally, outputs must always
be connected to a net. They
cannot be connected to a reg.
Stimulus Block

module stimulus;
reg clk;
reg reset;
wire[3:0] q;
// instantiate the design block
ripple-carry-counter rl(q, clk, reset);
// Control the clk signal that drives the design block.Cycle time = 10ns
initial
clk = 1'b0; //set clk to 0
always
Port Connection Rules

inouts
• Internally, inout ports
must always be of the
type net.
• Externally, inout ports
must always be connected
to a net.
Port Connection Rules
Width matching
• It is legal to connect internal and external items of
different sizes when making inter-module port
connections.
• However, a warning is typically issued that the widths
do not match.
Unconnected ports
• Verilog allows ports to remain unconnected.
fulladd4 fa0(SUM, , A, B, C_IN); // Output port c_out is unconnected
Example of illegal port connection
module Top;
• //Declare connection variables
reg [3:0]A,B;
reg C_IN;
reg [3:0] SUM;
wire C_OUT;
//Instantiate fulladd4, call it fa0
fulladd4 fa0(SUM, C_OUT, A, B, C_IN);
//Illegal connection because output port sum in module fulladd4
//is connected to a register variable SUM in module Top.
<stimulus>
• endmodule
 Example of illegal port connection
This problem is rectified if the variable SUM is declared as a net (wire).
Connecting Ports to External Signals

• There are two methods of making connections between

signals specified in the module instantiation and the
ports in a module definition.
• Connecting by ordered list
• Connecting ports by name
Connecting by ordered list

• The signals to be connected must appear in the module

instantiation in the same order as the ports in the port
list in the module definition.
 Connecting by ordered list
• module Top;
• module fulladd4(sum, c_out, a, • //Declare connection variables
b, c_in); • reg [3:0]A,B;
• output[3:0] sum; • reg C_IN;
• wire [3:0] SUM;
• output c_cout; • wire C_OUT;
• input [3:0] a, b; • //Instantiate fulladd4, call it
fa_ordered.
• input c_in; • //Signals are connected to ports in
• ... order (by position)
• fulladd4 fa_ordered(SUM, C_OUT, A,
• <module internals> B, C_IN);
• ...
• ...
• <stimulus>
• endmodule • ...
• endmodule
Connecting by ordered list
• module fulladd4(sum, c_out, a, b, c_in);
• fulladd4 fa_ordered(SUM, C_OUT, A, B, C_IN);
 Connecting by ordered list
• module Top;
• module fulladd4(sum, c_out, a, • //Declare connection variables
b, c_in); • reg [3:0]A,B;
• output[3:0] sum; • reg C_IN;
• wire [3:0] SUM;
• output c_cout; • wire C_OUT;
• input [3:0] a, b; • //Instantiate fulladd4, call it
fa_ordered.
• input c_in; • //Signals are connected to ports in
order (by position)
• ... • fulladd4
fa_byname(.c_out(C_OUT), .sum(SUM), .b
• <module internals> (B), .c_in(C_IN), .a(A),);
•
• ... ...
• <stimulus>
• endmodule • ...
• endmodule
Hierarchical Names
• Verilog supports a hierarchical design
methodology.
• Every module instance, signal, or variable is
defined with an identifier.
• A hierarchical name is a list of identifiers
separated by dots (".") for each level of hierarchy.
• Thus, any identifier can be addressed from any
place in the design by simply specifying the
complete hierarchical name of that identifier.
Chapter 5. Gate-Level
Modeling
Gate-Level Modeling

• At gate level, the circuit is described in terms of

gates (e.g., and, nand).
• Hardware design at this level requires basic
knowledge of digital logic design
Gate Types

• Verilog supports basic logic gates as predefined

primitives.
• These primitives are instantiated like modules
• They are predefined in Verilog and do not need a
module definition.
• There are two classes of basic gates:
and/or gates
buf/not gates
And/Or Gates
• And/or gates have one scalar output and multiple scalar
inputs.
• The first terminal in the list of gate terminals is an output
and the other terminals are inputs.
• The output of a gate is evaluated as soon as one of the
inputs changes.
and or xor
nand nor xnor
And/Or Gates
And/Or Gates
Gate Instantiation of And/Or Gates

wire OUT, IN1, IN2;

// basic gate instantiations.
and a1(OUT, IN1, IN2);
nand na1(OUT, IN1, IN2);
or or1(OUT, IN1, IN2);
nor nor1(OUT, IN1, IN2);
xor x1(OUT, IN1, IN2);
xnor nx1(OUT, IN1, IN2);
Gate Instantiation of And/Or Gates

// More than two inputs; 3 input nand gate

nand na1_3inp(OUT, IN1, IN2, IN3);
// gate instantiation without instance name
and (OUT, IN1, IN2); // legal gate instantiation
Buf/Not Gates
• Buf/not gates have one scalar input and one or more scalar
outputs.
• The last terminal in the port list is connected to the input. Other
terminals are connected to the outputs.
Two basic buf/not gate primitives are provided in Verilog.
buf not
 Not Gates
Buf Gates
Gate Instantiations of Buf/Not Gates

// basic gate instantiations.

buf b1(OUT1, IN);
not n1(OUT1, IN);
// More than two outputs
buf b1_2out(OUT1, OUT2, IN);
// gate instantiation without instance name
not (OUT1, IN); // legal gate instantiation
4-to-1 Multiplexer
Logic Diagram for Multiplexer
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3;
Verilog Description of Multiplexer
input s1, s0;
wire s1n, s0n;
wire y0, y1, y2, y3;
not (s1n, s1);
not (s0n, s0);
and (y0, i0, s1n, s0n);
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);
or (out, y0, y1, y2, y3);
endmodule
Stimulus for Multiplexer
module stimulus;
reg IN0, IN1, IN2, IN3;
reg S1, S0;
wire OUTPUT;
mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0);
initial
begin
IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
#5 S1 = 0; S0 = 0;
#5 S1 = 0; S0 = 1;
#5 S1 = 1; S0 = 0;
#5 S1 = 1; S0 = 1;
end
endmodule
The output of the simulation
• IN0= 1, IN1= 0, IN2= 1, IN3= 0
• S1 = 0, S0 = 0, OUTPUT = 1
• S1 = 0, S0 = 1, OUTPUT = 0
• S1 = 1, S0 = 0, OUTPUT = 1
• S1 = 1, S0 = 1, OUTPUT = 0
• 4-bit Ripple Carry Full Adder
Verilog Description for l-bit Full Adder
// Define a 1-bit full adder
module fulladd(sum, c_out, a, b, c_in);
output sum, c_out;
input a, b, c_in;
// Internal nets
wire s1, s2, c2;

xor (s1, a, b);

and (c1, a, b);
xor (sum, s1, c_in);
and (s2, s1, c_in);
or (c_out, s2, c1);
endmodule
// Define a 4-bit full adder
module fulladd4(sum, c_out, a, b, c_in);
output [3:0] sum;
output c_out;
input[3:0] a, b;
4-bit Ripple Carry Full
Adder
input c_in;
// Internal nets
wire c1, c2, c3;
fulladd fa0(sum[0], c1, a[0], b[0], c_in);
fulladd fa1(sum[1], c2, a[1], b[1], c1);
fulladd fa2(sum[2], c3, a[2], b[2], c2);
fulladd fa3(sum[3], c_out, a[3], b[3], c3);
endmodule
Stimulus for 4-bit Ripple Carry Full Adder
module stimulus;
// Set up variables
reg [3:0] A, B;
reg C_IN;
wire [3:0] SUM;
wire C_OUT;
fulladd4 FA1_4(SUM, C_OUT, A, B, C_IN);
Initial
begin
A = 4'd0; B = 4'd0; C_IN = 1'b0;
#5 A = 4'd3; B = 4'd4;
#5 A = 4'd2; B = 4'd5;
#5 A = 4'd9; B = 4'd9;
#5 A = 4'd10; B = 4'd15;
#5 A = 4'd10; B = 4'd5; C_IN = 1'b1;
end
initial
begin
$monitor($time," A= %b, B=%b, C_IN= %b, --- C_OUT= %b, SUM= %b\n",A, B, C_IN, C_OUT, SUM);
end
endmodule
 The output of the simulation is shown below.

0 A= 0000, B=0000, C_IN= 0, --- C_OUT= 0, SUM= 0000 A = 4'd0; B = 4'd0; C_IN = 1'b0;
5 A= 0011, B=0100, C_IN= 0, --- C_OUT= 0, SUM= 0111 #5 A = 4'd3; B = 4'd4;
10 A= 0010, B=0101, C_IN= 0, --- C_OUT= 0, SUM= 0111 #5 A = 4'd2; B = 4'd5;
15 A= 1001, B=1001, C_IN= 0, --- C_OUT= 1, SUM= 0010 #5 A = 4'd9; B = 4'd9;
20 A= 1010, B=1111, C_IN= 0, --- C_OUT= 1, SUM= 1001
#5 A = 4'd10; B = 4'd15;
25 A= 1010, B=0101, C_IN= 1 --- C_OUT= 1, SUM= 0000
#5 A = 4'd10; B = 4'd5; C_IN = 1'b1;
4-bit Ripple Carry Counter
module counter(Q , clock, clear);
output [3:0] Q;
input clock, clear;
// Instantiate the T flipflops
T_FF tff0(Q[0], clock, clear);
T_FF tff1(Q[1], Q[0], clear);
T_FF tff2(Q[2], Q[1], clear);
T_FF tff3(Q[3], Q[2], clear);
endmodule
Variables
Thank You