CS61C

Great Ideas
UC Berkeley
in UC Berkeley
Teaching Computer Architecture Teaching
Professor (a.k.a. Machine Structures) Professor
Dan Garcia Lisa Yan

Intro to RISC-V
(California Gold)

Garcia, Yan

cs61c.org
07-Intro to RISC-V(1)
 • Floating Point
Discussion
• The RISC-V Instruction
Floating Set Architecture
Point • Elements of
Architecture:
Discussion Registers
• Add/Sub Instructions
• Immediates Garcia, Yan

07-Intro to RISC-V(2)
 Floating Point Fallacy
 FP add associative? – 1.5 x
x
▫ x + (y + z) = –1.5x1038 + (1.5x1038 + 1.0) 1038
y 1.5 x 1038
= –1.5x1038 + (1.5x1038) = 0.0
▫ (x + y) + z = (–1.5x1038 + 1.5x1038) + 1.0 z 1.0
= (0.0) + 1.0 = 1.0
 Therefore, Floating Point add is not associative!
▫ Why? FP result approximates real result!
▫ With bigger exponents, step size between floats gets bigger,
too!
▫ This example: 1.5 x 1038 is so much larger than 1.0 that 1.5
x 1038 + 1.0 in floating point representation rounds to 1.5 x
1038. Garcia, Yan

07-Intro to RISC-V(3)
 Rounding Under the hood

 When we perform math on real numbers, we

have to worry about rounding to fit the result
in the significand field.
 The FP hardware carries two extra bits of
precision, and then rounds to get the proper
value
 Rounding also occurs when converting:
▫ double to a single precision value, or
▫ floating point number to an integer

Garcia, Yan

07-Intro to RISC-V(4)
 IEEE FP’s Four Rounding Modes
Under the hood

 Round towards +∞ Examples in decimal

▫ ALWAYS round “up”: 2.001  3, -2.001  -2 (but applies to IEEE754
binary)
 Round towards –∞
▫ ALWAYS round “down”: 1.999  1, -1.999  -2
 Truncate
▫ Just drop the last bits (round towards 0)
 (default) Unbiased. If midway, round to even
▫ Normal rounding, almost: 2.4  2, 2.6  3, 2.5  2, 3.5  4
▫ Round like you learned in grade school (nearest representable
number)…
▫ …except if the value is right on the borderline, in which case we
round to the nearest EVEN number
▫ Ensures fairness on calculation, balances out inaccuracies. Garcia, Yan

07-Intro to RISC-V(5)
▪
 FP Addition Under the hood

 More difficult than with integers

 Can’t just add significands…
 How do we do it?
▫ De-normalize to match exponents
▫ Add significands together
▫ Keep the matched exponent
▫ Normalize (possibly changing exponent)
 Note: If signs differ, just perform a subtract
instead.
Garcia, Yan

07-Intro to RISC-V(6)
 Casting floats to ints and vice
versa
(int) floating_point_expression
Coerces and converts floating point to nearest
integer
(C uses truncation).
i = (int) (3.14159 * f);

(float) integer_expression
Converts integer to nearest floating point.
f = f + (float) i;
Garcia, Yan

07-Intro to RISC-V(7)
 Double Casting Doesn’t Always
Work
int i = …;
if (i == (int)((float) i))
{
printf("true");
}

 Will not always print

“true”!
 Most large values of
integers don’t have exact
floating point
representations.
▫ Recall: only 223 floats per
exponent
 What about double? Garcia, Yan

07-Intro to RISC-V(8)
 Double Casting Doesn’t Always
Work
int i = …; float f = …;
if (i == (int)((float) i)) if (f == (float)((int) f))
{ {
printf("true"); printf("true");
} }

 Will not always print  Will not always print

“true”! “true”!
 Most large values of
 Small floating point
integers don’t have exact
floating point numbers (<1) don’t have
representations. integer representations.
▫ Recall: only 223 floats per  For other numbers,
exponent
rounding errors…
 What about double? Garcia, Yan

07-Intro to RISC-V(9)
Now you can make float jokes
too…

Saturday Morning
Breakfast
Comics
Side www.smbc-comics.com/comic/2013-06-05
note: the robot is using IEEE 754 double-precision.
(double) 0.3:
0.29999999999999999
(double) 0.1 + (double) 0.2:
0.30000000000000004 Garcia, Yan

07-Intro to RISC-V(10)
(change of gears)

Garcia, Yan

07-Intro to RISC-V(11)
 • Floating Point
Discussion
The RISC-V • The RISC-V Instruction
Instruction Set Architecture
Set • Elements of
Architecture:
Architectur Registers
e • Add/Sub Instructions
• Immediates Garcia, Yan

07-Intro to RISC-V(12)
Great Idea #1: Abstraction
(Levels of Representation/Interpretation)
High Level Language temp = v[k];
v[k] = v[k+1];
Program (e.g., C) v[k+1] = temp;
Compiler Anything can be
lw x3, 0(x10)
Assembly Language lw x4, 4(x10) represented
Program (e.g., RISC-V) sw
sw
x4,
x3,
0(x10)
4(x10)
as a number,
i.e., data or instructions
Assembler 1000 1101 1110 0010 0000 0000 0000 0000
Machine Language 1000 1110 0001 0000 0000 0000 0000 0100
Program (RISC-V) 1010 1110 0001 0010 0000 0000 0000 0000
1010 1101 1110 0010 0000 0000 0000 0100

Hardware Architecture Description 1

+4
wb
Da e
R [
]
pc

Reg[rs1]
1
A
al
u
pc+4

(e.g., block diagrams)

al
p ta
inst[11:7] Ad g 0 D 1
u
pc+4
0 IM D Reg[rs2] L A
M Da
wb
c E inst[19:15] dr
AddrA Da
Bra 0 d 0
D
ta
nc
Co U Da E
dr
ta mem
1 R
M inst[24:20] Ad Da h ta

Architecture Implementation
m
W M
dr A
ta p.
B B

Logic Circuit Description

inst[31:7]
I . imm[31:0]
G
m
em

(Circuit Schematic Diagrams) n

Garcia, Yan

07-Intro to RISC-V(13)
 Assembly Language
 Basic job of a CPU: execute lots of instructions.
 Instructions are the primitive operations that
the CPU may execute.
▫ Like a sentence: operations (verbs) applied to operands
(objects), processed in sequence …
 Different CPUs implement different sets of
instructions. The set of instructions a
particular CPU implements is an Instruction Set
Architecture (ISA).
▫ Examples: ARM (cell phones), Intel x86 (i9, i7, i5, i3),
IBM/Motorola PowerPC (old Macs), MIPS, RISC-V, ...
Garcia, Yan

07-Intro to RISC-V(14)
 Book: Programming From the
Ground Up
“A new book was just released which is based on a new
concept – teaching computer science through assembly
language (Linux x86 assembly language, to be exact). This
book teaches how the machine itself operates, rather than
just the language. I've found that the key difference between
mediocre and excellent programmers is whether or not they
know assembly language. Those that do tend to understand
computers themselves at a much deeper level. Although
[almost!] unheard of today, this concept isn't really all that
new -- there used to not be much choice in years past. Apple
computers came with only BASIC and assembly language,
and there were books available on assembly language for
kids. This is why the old-timers are often viewed as 'wizards':
they had to know assembly language programming.”
-- slashdot.org comment, 2004-02-05

Garcia, Yan

07-Intro to RISC-V(15)
 Instruction Set Architectures
 Early trend was to add more and more instructions to
new CPUs to do elaborate operations.
▫ VAX architecture had an instruction to multiply polynomials!
 Reduced Instruction Set Computer (RISC) philosophy:
▫ Cocke IBM, Patterson, Hennessy, 1980s.
▫ Keep the instruction set small and simple, makes it easier to build
fast hardware.
▫ Let software do complicated operations by composing simpler
ones.
▫ This went against the conventional wisdom of the time.
(he who laughs last, laughs best)

Garcia, Yan

07-Intro to RISC-V(16)
 Patterson and Hennessy win
Turing!

https://engineering.berkeley.edu/news/2018/06/patterson-wins-turing-award/ Garcia, Yan

07-Intro to RISC-V(17)
 RISC-V Architecture IBM 360 Green Card

 New open-source, license-free ISA spec

▫ Supported by growing shared software ecosystem
▫ Appropriate for all levels of computing system,
from microcontrollers to supercomputers
▫ 32-bit, 64-bit, and 128-bit variants
(class/textbook uses 32-bit)
 Why RISC-V instead of Intel x86-64?
▫ RISC-V is simple and elegant.
We don’t need to get bogged down in gritty details.
▫ RISC-V has exponential adoption,
from microcontrollers to CPUs to
warehouse-scale computers.
https://cs61c.org/  Resources RISC-V Green Card Garcia, Yan

07-Intro to RISC-V(18)
 RISC-V Origins
 Started in Summer 2010 to support
open research and teaching at
UC Berkeley
▫ Lineage can be traced to RISC-I/II projects (1980s) RISC-I
 As the project matured, it migrated
to RISC-V foundation (www.risc-v.org)
 Many commercial and research projects
RISC-II
based on RISC-V.
▫ Open-source and proprietary
▫ Widely used in education
 Read more:
▫ https://riscv.org/risc-v-history/
▫ https://riscv.org/risc-v-genealogy/ Garcia, Yan

07-Intro to RISC-V(19)
 • Floating Point
Discussion
Elements • The RISC-V Instruction
of Set Architecture
Architectur • Elements of
Architecture:
e: Registers
Registers • Add/Sub Instructions
• Immediates Garcia, Yan

07-Intro to RISC-V(20)
 Instruction Set

“instruction sets”

 Instruction set for a particular

architecture (e.g. RISC-V) is
represented by the assembly language.
add x1, x2, x3
 Each line of assembly code
represents one instruction for the operatio registers
computer. n name
Garcia, Yan

07-Intro to RISC-V(21)
 Higher-Level Language vs. Assembly Language (1/2)

C, Java RISC-V
 In C (and most high-level  Assembly operands are
languages), variables declared registers.
first and given a type. ▫ Registers are limited number of special
locations, built directly into the
▫ int fahr, celsius;
hardware.
char a, b, c, d, e;
▫ RISC-V: Operations can only be
 Each variable can ONLY performed on register operands.
represent a value of the type it  In assembly language, the
was declared as (cannot registers have no type.
mix/match int/char variables). ▫ Register contents are just bits.

 In high-level languages,  Operation determines “type,” i.e.,

variable types determine how register contents are
operation. treated.
▫ E.g., as value, memory address, etc.
▫ int *p = …; Garcia, Yan
p = p + 2; 07-Intro to RISC-V(22)
 Registers are Inside the
Processor
Processor Memory
Enable? Input
Benefit:
Control Read/ Write
Since registers
are directly in
Address
Datapath hardware,
ProgramCounter (PC) Bytes
they’re very
Registers fast
Write Data (faster than
0.25ns).
Read Data
Arithmetic-Logic Output ▫ Speed of light:
Unit (ALU)
3x108m/s =
0.3m/ns =
30cm/ns
Processor-Memory Interface I/O-Memory Interfaces = 10cm/0.3ns!!!
Garcia, Yan

07-Intro to RISC-V(23)
 Great Idea #3: Principle of Locality / Memory Hierarchy

Processor Extremely fast

chip Extremely
expensive
Tiny capacity

Storage
Latency
Analogy

Garcia, Yan

07-Intro to RISC-V(24)
 32 Registers in RISC-V
 Drawback: Each ISA a predetermined number of
registers.
▫ Why? Registers are built into hardware.
▫ Solution: RISC-V code must be very carefully put together to
efficiently use registers.
▪ Nowadays: compiler maps C variables to RISC-V registers across declarations,
function calls, etc.
 32 registers in RISC-V.
▫ Why 32? Smaller is faster, but too small is bad.
▫ Goldilocks principle (“This porridge is too hot; This porridge is too
cold; this porridge is just right”)
 Each RISC-V register is 32 bits wide (in RV32 variant).
▫ Groups of 32 bits called a word in RV32. Garcia, Yan

07-Intro to RISC-V(25)
 Register Names and Numbers
 Registers are numbered from 0 to 31.
▫ Referred to by number x0 – x31.
 x0 is special, always holds value zero.
▫ So only 31 registers able to hold variable values.
 Each register can be referred to by number or name.
▫ We’ll explain names next week.
 Ok, enough already…gimme my RV32!!!

Garcia, Yan

07-Intro to RISC-V(26)
 • Floating Point
Discussion
• The RISC-V Instruction
Add/Sub Set Architecture
Instruction • Elements of
Architecture:
s Registers
• Add/Sub Instructions
• Immediates Garcia, Yan

07-Intro to RISC-V(27)
 Higher-Level Language vs. Assembly Language (2/2)

C, Java RISC-V
 Each line can contain  Each statement is an instruction.
▫ An instruction executes exactly one
multiple operations. short list of simple commands.
a = b * 2 - (arr[2] + *p);  Each line of assembly code
 Common operations are: contains at most 1 instruction.
▫ =, +, –, *, / add x1, x2, x3
sub x1, x1, x4
▫ Here, * includes both multiply
and dereference
The compiler translates from higher-
level language down to assembly…
…so RISC-V instructions are often
closely related to common C/Java
operations.
Garcia, Yan

07-Intro to RISC-V(28)
 RISC-V Arithmetic Instruction
Syntax
opname rd, rs1, rs2
operatio ”destinatio ”source1” ”source2”
n, by n” 1st 2nd
name operand operand for operand for
getting operation operation
result
 Syntax is rigid:
▫ 1 operator, 3 operands.
▫ Why? Keep hardware simple via regularity. (more in a few
weeks)

Garcia, Yan

07-Intro to RISC-V(29)
 RISC-V Addition and Subtraction
opname rd, rs1, rs2
operatio ”destinatio ”source1” ”source2”
n, by n” 1st 2nd
name operand operand for operand for
getting operation operation
 Addition
result  Subtraction
RISC-V add x1,x2,x3 RISC-V sub x4,x5,x6
(remember!
C a = b + c; C d = e – f; order of
operands
matter in sub)

Garcia, Yan

07-Intro to RISC-V(30)
 RISC-V Arithmetic, Example 1
 How could we translate this C statement?
a = b + c + d - e;

x10 x1 x2 x3 x4
▫ Assume the above mapping for C variables ↔︎RISC-V registers.

 Solution: Break into multiple instructions!

add x10, x1, x2 # a_temp = b + c
add x10, x10, x3 # a_temp = a_temp + d
sub x10, x10, x4 # a = a_temp - e

A single line of C may In-line comments prefixed by #, work like

break up into several lines C99’s //.
of RISC-V. Unlike C, no multi-line comment (/* */) Garcia, Yan
support.
07-Intro to RISC-V(31)
 RISC-V Arithmetic, Example 2
 How do we do this?
f = (g + h) - (i + j);
x19 x20 x21 x22 x23 x5 x6
▫ Assume the above mapping for C variables ↔︎RISC-V registers.
 Solution: Use intermediate temporary registers!
add x5, x20, x21 # a_temp = g + h
add x6, x22, x23 # b_temp = i + j
sub x19, x5, x6 # f = (g + h)- (i + j)
 Note: A good compiler may actually do the following.
Why? Can use zero temp
registers!
f = g + h - i - j;
Garcia, Yan

07-Intro to RISC-V(32)
 Aside: Apollo Guidance Computer
 Margaret Hamilton
Director of Software Engineering
Division of MIT Instrumentation
Laboratory
▫ Built Apollo Guidance Computer
Command Module (navigation, lunar landing)
▪ 72KB of memory on board Eagle (Apollo 11, 1969)
Margaret Hamilton
and Apollo code
Wikimedia Commons

Presidenti
al Medal
of
Freedom
ignition file (2016)
https://abcnews.go.com/Technology/apollo-11s-source-code-tons-easter-eggs-i Garcia, Yan
ncluding/story?id=40515222
07-Intro to RISC-V(33)
 • Floating Point
Discussion
• The RISC-V Instruction
Set Architecture
Immediate • Elements of
s Architecture:
Registers
• Add/Sub Instructions
• Immediates Garcia, Yan

07-Intro to RISC-V(34)
 Immediates
 Immediates are numerical constants.
▫ They appear often in code; hence, they have separate instructions.
 Add Immediate instruction:
RISC-V addi x3,x4,10 Syntax similar to add instruction. But
the
C f = g + 10; last operand must be a number, not a
register.

Garcia, Yan

07-Intro to RISC-V(35)
 Immediates
 Immediates are numerical constants.
▫ They appear often in code; hence, they have separate instructions.
 Add Immediate instruction:
RISC-V addi x3,x4,10 Syntax similar to add instruction. But
the
C f = g + 10; last operand must be a number, not a
register.
 There is no Subtract Immediate instruction in RISC-V.
Why?
RISC Philosophy: Reduce the possible
▫ While there are add
RISC-V addi x3,x4,-10 and sub instructions, to subtract an immediate,
types of operations to an absolute
just use addi:
minimum.
C f = g - 10; If an operation can be decomposed
into a simpler operation, don’t include
it in the ISA. Garcia, Yan

07-Intro to RISC-V(36)
 Register Zero
 One particular immediate, the number zero (0),
appears very often in code.
 RISC-V hardwires the register zero (x0) to value 0:
RISC-V add x3,x4,x0

C f = g;

RISC-V addi x3,x0,0xff

C f = 0xff;
 Defined in hardware, so an instruction add
x0,x3,x4
will not do anything! Garcia, Yan

07-Intro to RISC-V(37)
 Concept Check: True or False?
1. Types are associated with declaration in C
(normally), but are associated with instructions
(operators) in RISC-V.
2. Since there are only 32 registers, we can’t write
RISC-V for C expressions that contain > 32
variables. 123
A. FFF
3. If p (stored in x9) were a pointer to an array of B. FFT
ints, C. FTF
D. FTT
then p++; would be E. TFF
addi x9 x9 1 F. TFT
G. TTF
H. TTT
Garcia, Yan

07-Intro to RISC-V(38)
 Concept Check: True or False?
1. Types are associated with declaration in C
(normally), but are associated with instructions
(operators) in RISC-V.
2. Since there are only 32 registers, we can’t write
RISC-V for C expressions that contain > 32
variables. 123
A. FFF
3. If p (stored in x9) were a pointer to an array of B. FFT
ints, C. FTF
D. FTT
then
1. True, we p++; would
saw that on an be
earlier slide. E. TFF
addi
2. False. wex9
sawx9how1 to break up longer equations to smaller F. TFT
ones already. G. TTF
H. TTT
3. False. Don’t forget that ints are (usually) 4 bytes wide, so
instruction would be addi x9, x9, 4. Garcia, Yan

07-Intro to RISC-V(39)