UNIT-3

Data Logic Cells

Data Path Elements, Adders, Multiplier,
Arithmetic Operator, I/O cell, Cell Compilers.
 What is Data Path
• A datapath is a collection of functional units, as
arithmetic logic units or multipliers, that perform
data processing operations.
• It is a central part of many
central processing units(CPUs) along with the
control unit, which largely regulates interaction
between the datapath and the data itself, usually
stored in registers or main memory.
 Data Path Logic Cells
• Datapath layout automatically takes care of
most
of the interconnect between the cells with the
following advantages:
– Regular layout produces predictable and equal
delay for each bit.
– Interconnect between cells can be built into
each cell.
Digital Device Components
Why Datapaths?
• The speed of these elements often dominates
the overall system performance so optimization
techniques are important.
• However, as we will see, the task is non-trivial
since there are multiple equivalent logic and
circuit topologies to choose from, each with
adv./disadv. in terms of speed, power and area.
BIT SLICING
 Datapath Elements
• Shifters
• Adders
• Multipliers
SHIFTER
VERILOG CODE
module shifter(Con,A,Y);
input [1:0] Con;
input[2:0] A;
output[2:0] Y;
reg [2:0] Y;
always @(A or Con)
begin
case(Con)
0: Y=A;
1: Y=A<<1;(LEFT)
2: Y=A>>1;(RIGHT)
default: Y=3’b0;
endcase
end
endmodule
Combinational logic shifters with
shiftin and shiftout
Verilog Code
• always@(Sel or A or ShiftLeftIn or ShiftRightIn);
begin
• A_wide={ShiftLeftIn,A,ShiftRightIn};
• case(Sel)
• 0: Y_wide=A_wide;
• 1: Y_wide=A_wide<<1;
• 2: Y_wide=A_wide>>1;
• 3:Y_wide=5’b0;
• default: Y=A_wide;
• endcase
• ShiftLeftOut=Y_wide[0];
• Y=Y_wide[2:0];
• ShiftRightOut=Y_wide[4];
• end
Combinational 6 bit Barrel Shifter
 Verilog Coding
function [2:0] rotate_left;
• input [5:0] A;
• input [2:0] NumberShifts;
• reg [5:0] Shifting;
• integer N;
• begin
• Shifting = A;
• for(N=1;N<=NumberShifts;N=N+1)
• begin
• Shifting={Shifting[4:0],Shifting[5])};
• end
• rotate_left=Shifting;
• end
• endfunction
• always @(Rotate or A)
• begin
• case(Rotate)
• 0: Y=A;
• 1: Y=rotate_left(A,1);
• 2: Y=rotate_left(A,2);
• 3: Y=rotate_left(A,3);
• 4: Y=rotate_left(A,4);
• 5: Y=rotate_left(A,5);
• default: Y=6’bx;
• endcase
• end
Single-Bit Addition
 Full adder
• Computes one-bit sum, carry:
• – si = ai XOR bi XOR ci
• – ci+1 = aibi + aici + bici
• Half adder computes two-bit sum.
• Ripple-carry adder: n-bit adder built from
• full adders.
• Delay of ripple-carry adder goes through
• all carry bits.
 Carry-Ripple Adder
• Simplest design: cascade full adders
• – Critical path goes from Cin to Cout
• – Design full adder to have fast carry delay
 Verilog for full adder
• module fulladd(a,b,carryin,sum,carryout);
• input a, b, carryin; /* add these bits*/
• output sum, carryout; /* results */
• assign {carryout, sum} = a + b + carryin;
• /* compute the sum and carry */
• endmodule
 Verilog for ripple-carry adder
• module nbitfulladd(a,b,carryin,sum,carryout)
• input [7:0] a, b; /* add these bits */
• input carryin; /* carry in*/
• output [7:0] sum; /* result */
• output carryout;
• wire [7:1] carry; /* transfers the carry between bits */
• fulladd a0(a[0],b[0],carryin,sum[0],carry[1]);
• fulladd a1(a[1],b[1],carry[1],sum[1],carry[2]);
• fulladd a7(a[7],b[7],carry[7],sum[7],carryout]);
• endmodule
Generate and Propagate
Carry-lookahead adder
• First compute carry propagate, generate:
• – Pi = ai + bi
• – Gi = ai bi
• Compute sum and carry from P and G:
• – si = ci XOR Pi XOR Gi
• – ci+1 = Gi + Pici
• Can recursively expand carry formula:
• – ci+1 = Gi + Pi(Gi-1 + Pi-1ci-1)
• – ci+1 = Gi + PiGi-1 + PiPi-1 (Gi-2 + Pi-1ci-2)
• • Expanded formula does not depend on
• intermerdiate carries.
• Allows carry for each bit to be computed
• independently.
Depth-4 carry-lookahead
• As we look ahead further logic becomes
complicated.
• Takes longer to compute
• Becomes less regular.
• There is no similarity of logic structure in
each cell.
• We have developed CLA adders, like
• Brent-Kung adder
 Carry-skip adder
• Looks for cases in which
carry out of a set of bits is
identical to carry in.
• Typically organized into b-bit stages.
• Can bypass carry through all stages in a
group when all propagates are true: Pi Pi+1
…Pi+b-1.
– Carry out of group when carry out of last bit in
group or carry is bypassed.
 CARRY SKIP MECHANISM

A carry-skip adder (also known as a carry-bypass adder) is an adder

implementation that improves on the delay of a ripple-carry adder
with little effort compared to other adders. The improvement of the
worst-case delay is achieved by using several carry-skip adders to form
a block-carry-skip adder.
 Carry-select adder
• Computes two results in parallel, each for
• different carry input assumptions.
• Uses actual carry in to select correct result
• Reduces delay to multiplexer
 Carry-save adder
• Useful in multiplication.
• Input: 3 n-bit operands.
• Output: n-bit partial sum, n-bit carry.
– Use carry propagate adder for final sum.
• Operations:
– s = (x + y + z) mod 2.
– c = [(x + y + z) –2] / 2.
 ALUs
• ALU computes a variety of logical and
• arithmetic functions based on opcode.
• May offer complete set of functions of two
• variables or a subset.
• ALU built around adder, since carry chain
• determines delay.
 I/O Cells
• I/O pads are specalized to
connect to the actual pins of the
device
– Electrostatic discharge (ESD)
– High(er) drive capability to drive
larger capacitances (bonding
pad, bond wire, device pin, PCB
trace > 20pF)
• Different types of I/O pads are
provided to perform different
functions
– Digital input
– Digital Output
– Digital Bi-directional
A tri-state bidirectional output buffer with I/O pad.
– Analog In/Output
 CELL COMPILERS
The process of hand crafting circuits and layout for a full-custom
IC is a tedious, time-consuming, and error-prone task.
There are two types of automated layout assembly tools, often
known as a silicon compilers .
The first type produces a specific kind of circuit, a RAM
compiler ormultiplier compiler , The second type of compiler is
more flexible, usually providing a programming language that
assembles or tiles layout from an input command file, but this is
full-custom IC design.
We can build a register file from latches or flip-flops, but, at 4.5–
6.5 gates (18–26 transistors) per bit, this is an expensive way to
build memory.
Dynamic RAM (DRAM) can use a cell with only one transistor,
storing charge on a capacitor that has to be periodically refreshed
as the charge leaks away.
ASIC RAM is invariably static (SRAM), so we do not need to refresh
the bits.
When we refer to RAM in an ASIC environment we almost always
mean SRAM.
Most ASIC RAMs use a six-transistor cell (four transistors to form
two cross-coupled inverters that form the storage loop, and two
more transistors to allow us to read from and write to the cell).
RAM compilers are available that produce single-port RAM (a
single shared bus for read and write) as well as dual-port RAMs ,
and multiport RAMs .
In a multi-port RAM the compiler may or may not handle the
problem of address contention (attempts to read and write to the
same RAM address simultaneously).
RAM can beasynchronous (the read and write cycles are triggered
by control and/or address transitions asynchronous to a clock)
or synchronous (using the system clock).
In addition to producing layout we also need a model compiler so
that we can verify the circuit at the behavioral level, and we need a
netlist from a netlist compiler so that we can simulate the circuit
and verify that it works correctly at the structural level.
Silicon compilers are thus complex pieces of software.
We assume that a silicon compiler will produce working silicon even
if every configuration has not been tested.
This is still ASIC design, but now we are relying on the fact that the
tool works correctly and therefore the compiled blocks are correct
by construction .