Linked list RTL

Cyclone V FPGA

Cyclone V FPGA

RD_DATA
ROM FPGA GPIO PINS ll_req/resp interface
ROM_DMA_ENGINE ll_engine
RD_REQ
Operations supported
• Read ll regs -> 0. total no. of nodes,
1. no. Of node of a particular linked list,
2. no. of active lls,
3. active lls reg – bitwise indication of currently active ll_nums
4. Max no. lls
• Insert -> at head, at tail, at node number
• Delete (no Read) -> at head, at tail, at node number
• Config HeadPtrMem -> set num of linked lists, set each head pointer, delete linked list
• Update Node value -> @Head, @Tail, @nodeNum
• Read Node value -> @Head, @Tail, @nodeNum
• Pop (Read n Delete) value -> @Head, @Tail, @nodeNum
• Empty Linked list (Delete all nodes) -> all lists, a specific list
 Insert at head Insert at node num (2)
ll_num
Update hd_ptr nxt_ptr nxt_ptr nxt_ptr Insert at tail
0

nxt_ptr Delete at tail

1 nxt_ptr nxt_ptr

2 hd_ptr nxt_ptr nxt_ptr nxt_ptr

Mem
. .
. . Delete a middle node
. .
. . Delete head node

N-1 Update hd_ptr nxt_ptr nxt_ptr nxt_ptr

N Hd_ptr not used

 Upd nxt_avail_ptrs corresponding to hdptr being confgd.
ll_engine_top – block diagram
Update avail ptrs
Fwd decoded I/p wr_ctrl nxt avail. ptr nxt_ptr_srvr
I/ req. to exec unit
ll_op_decode_unit
P from
DMA
W
Resp. Gen ll_mngr fsm control interface data_mem nxt_ptr
indication after reqstd. ll_mngr to wr and rd ctrl units
operation is done
R

Resp. to W R R W rd_ctrl
DMA ll_resp_gen_unit
Legends
node_c - memory
hd_ptr
ntr
- logic
- interface
- 1-bit signal
Multi-list insertion
at tail
Write to tail sequence
1. Read the hdptr and ll_cntr mem @location: ll_num

2. request read controller to read out the nxtptr mem, counter down from
ll_cntr value -> loop { rd nxtptr; ll_cntr_int--} till (ll_cntr_int > 0)

3. With the final nxtptr_wr value; write dataMem location:@nxtptr_wr and get
nxtptr_avail from nxtptr_srvr and wr that value @nxtptr_wr location of
nxtptrMem

4. Once wr_ctrl is done, ll_mngr can update the ll_cntr mem value, send out
response and release the decoder
0 data_mem
1 data_mem
nxt_ptr 0 nxt_ptr_srvr 1
2 data_mem
0-0 0
nxt_ptr 1
3 data_mem nxt_ptr 2
4 data_mem nxt_ptr 3
5 data_mem nxt_ptr 4
nxt_ptr 5
6 data_mem 0
nxt_ptr 6
7 data_mem
5 nxt_ptr 7
8 data_mem nxt_ptr 8
6
9 data_mem nxt_ptr 9
10 data_mem 15 nxt_ptr 10
nxt_ptr 11
11 data_mem
nxt_ptr 12
12 data_mem
nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem nxt_ptr 15
15 data_mem nxt_ptr 16
0 0-0
1 data_mem
1 0 nxt_ptr_srvr 2
2 data_mem
5-0 5
nxt_ptr 1
3 data_mem nxt_ptr 2
4 data_mem nxt_ptr 3
5 data_mem nxt_ptr 4
nxt_ptr 5
6 data_mem 0
nxt_ptr 6
7 data_mem
5 nxt_ptr 7
8 data_mem nxt_ptr 8
6
9 data_mem nxt_ptr 9
10 data_mem 15 nxt_ptr 10
nxt_ptr 11
11 data_mem
nxt_ptr 12
12 data_mem
nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem nxt_ptr 15
15 data_mem nxt_ptr 16
0 0-0
1 data_mem
1 0 nxt_ptr_srvr 3
2 data_mem
6-0 6
nxt_ptr 1
3 data_mem nxt_ptr 2
4 data_mem nxt_ptr 3
5 5-0 nxt_ptr 4
2 5
6 data_mem 0
nxt_ptr 6
7 data_mem
5 nxt_ptr 7
8 data_mem nxt_ptr 8
6
9 data_mem nxt_ptr 9
10 data_mem 15 nxt_ptr 10
nxt_ptr 11
11 data_mem
nxt_ptr 12
12 data_mem
nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem nxt_ptr 15
15 data_mem nxt_ptr 16
0 0-0
1 data_mem
1 0 nxt_ptr_srvr 4
2 data_mem
15-0 15
nxt_ptr 1
3 data_mem nxt_ptr 2
4 data_mem nxt_ptr 3
5 5-0 nxt_ptr 4
2 5
6 6-0 0
3 6
7 data_mem
5 nxt_ptr 7
8 data_mem nxt_ptr 8
6
9 data_mem nxt_ptr 9
10 data_mem 15 nxt_ptr 10
nxt_ptr 11
11 data_mem
nxt_ptr 12
12 data_mem
nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem nxt_ptr 15
15 data_mem nxt_ptr 16
0 0-0
1 data_mem
1 0 nxt_ptr_srvr 7
2 data_mem
6-1 6
nxt_ptr 1
3 data_mem nxt_ptr 2
4 data_mem nxt_ptr 3
5 5-0 nxt_ptr 4
2 5
6 6-0 0
3 6
7 data_mem
5 nxt_ptr 7
8 data_mem nxt_ptr 8
6
9 data_mem nxt_ptr 9
10 data_mem 15 nxt_ptr 10
nxt_ptr 11
11 data_mem
nxt_ptr 12
12 data_mem
nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem 4 15
15 15-0 nxt_ptr 16
0 0-0
1 data_mem
1 0 nxt_ptr_srvr 8
2 data_mem
0-1 0
nxt_ptr 1
3 6-1 nxt_ptr 2
4 data_mem 7 3
5 5-0 nxt_ptr 4
2 5
6 6-0 0
3 6
7 data_mem
5 nxt_ptr 7
8 data_mem nxt_ptr 8
6
9 data_mem nxt_ptr 9
10 data_mem 15 nxt_ptr 10
nxt_ptr 11
11 data_mem
nxt_ptr 12
12 data_mem
nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem 4 15
15 15-0 nxt_ptr 16
0 0-0
1 0-1
1 0 nxt_ptr_srvr 9
2 data_mem
6-2 6
8 1
3 6-1 nxt_ptr 2
4 data_mem 7 3
5 5-0 nxt_ptr 4
2 5
6 6-0 0
3 6
7 data_mem
5 nxt_ptr 7
8 data_mem nxt_ptr 8
6
9 data_mem nxt_ptr 9
10 data_mem 15 nxt_ptr 10
nxt_ptr 11
11 data_mem
nxt_ptr 12
12 data_mem
nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem 4 15
15 15-0 nxt_ptr 16
0 0-0
1 0-1
1 0 nxt_ptr_srvr 10
2 data_mem
5-1 5
8 1
3 6-1 nxt_ptr 2
4 data_mem 7 3
5 5-0 nxt_ptr 4
2 5
6 6-0 0
3 6
7 6-2
5 9 7
8 data_mem nxt_ptr 8
6
9 data_mem nxt_ptr 9
10 data_mem 15 nxt_ptr 10
nxt_ptr 11
11 data_mem
nxt_ptr 12
12 data_mem
nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem 4 15
15 15-0 nxt_ptr 16
0 0-0
1 0-1
1 0 nxt_ptr_srvr 11
2 5-1
15-1 15
8 1
3 6-1 10 2
4 data_mem 7 3
5 5-0 nxt_ptr 4
2 5
6 6-0 0
3 6
7 6-2
5 9 7
8 data_mem nxt_ptr 8
6
9 data_mem nxt_ptr 9
10 data_mem 15 nxt_ptr 10
nxt_ptr 11
11 data_mem
nxt_ptr 12
12 data_mem
nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem 4 15
15 15-0 nxt_ptr 16
0 0-0
1 0-1
1 0 nxt_ptr_srvr 12
2 5-1
0-2 0
8 1
3 6-1 10 2
4 15-1 7 3
5 5-0 11 4
2 5
6 6-0 0
3 6
7 6-2
5 9 7
8 data_mem nxt_ptr 8
6
9 data_mem nxt_ptr 9
10 data_mem 15 nxt_ptr 10
nxt_ptr 11
11 data_mem
nxt_ptr 12
12 data_mem
nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem 4 15
15 15-0 nxt_ptr 16
0 0-0
1 0-1
1 0 nxt_ptr_srvr 13
2 5-1
0-3 0
8 1
3 6-1 10 2
4 15-1 7 3
5 5-0 11 4
2 5
6 6-0 0
3 6
7 6-2
5 9 7
8 0-2 12 8
6
9 data_mem nxt_ptr 9
10 data_mem 15 nxt_ptr 10
nxt_ptr 11
11 data_mem
nxt_ptr 12
12 data_mem
nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem 4 15
15 15-0 nxt_ptr 16
0 0-0
1 0-1
1 0 nxt_ptr_srvr -
2 5-1
15-2 15
8 1
3 6-1 10 2
4 15-1 7 3
5 5-0 11 4
2 5
6 6-0 0
3 6
7 6-2
5 9 7
8 0-2 12 8
6
9 data_mem nxt_ptr 9
10 5-2 15 14 10
nxt_ptr 11
11 data_mem
13 12
12 0-3
nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem 4 15
15 15-0 nxt_ptr 16
0 0-0
1 0-1
1 0 nxt_ptr_srvr -
2 5-1
15-3 15
8 1
3 6-1 10 2
4 15-1 7 3
5 5-0 11 4
2 5
6 6-0 0
3 6
7 6-2
5 9 7
8 0-2 12 8
6
9 data_mem nxt_ptr 9
10 5-2 15 14 10
- 11
11 15-2
13 12
12 0-3
nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem 4 15
15 15-0
0 0-0
1 0-1
1 0 nxt_ptr_srvr -
2 5-1
6-3 6 8 1
3 6-1 10 2
4 15-1 7 3
5 5-0 11 4
2 5
6 6-0 0
3 6
7 6-2
5 9 7
8 0-2 12 8
6
9 data_mem nxt_ptr 9
10 5-2 15 14 10
- 11
11 15-2
13 12
12 0-3
nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem 4 15
15 15-0
0 0-0
1 0-1
1 0 nxt_ptr_srvr -
2 5-1
5-3 6 8 1
3 6-1 10 2
4 15-1 7 3
5 5-0 11 4
2 5
6 6-0 0
3 6
7 6-2
5 9 7
8 0-2 12 8
6
9 6-3 - 9
10 5-2 15 14 10
- 11
11 15-2
13 12
12 0-3
nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem 4 15
15 15-0
0 0-0
1 0-1
1 0 nxt_ptr_srvr -
2 5-1
0-4 0 8 1
3 6-1 10 2
4 15-1 7 3
5 5-0 11 4
2 5
6 6-0 0
3 6
7 6-2
5 9 7
8 0-2 12 8
6
9 6-3 - 9
10 5-2 15 14 10
- 11
11 15-2
13 12
12 0-3
nxt_ptr 13
13 data_mem - 14
14 5-3 4 15
15 15-0
0 0-0
1 0-1
1 0 nxt_ptr_srvr -
2 5-1
0-4 0 8 1
3 6-1 10 2
4 15-1 7 3
5 5-0 11 4
2 5
6 6-0 0
3 6
7 6-2
5 9 7
8 0-2 12 8
6
9 6-3 - 9
10 5-2 15 14 10
- 11
11 15-2
13 12
12 0-3
- 13
13 0-4 - 14
14 5-3 4 15
15 15-0
Insertion at Node
number
Step 1 6 6-0 | 3 6-1 | 7 6-2 | 9

Insert req-> 6-3 | at 2 6-2 | tmp

Step 2 6 6-0 | 3 6-1 | 7 6-2 | 9

Node num-> 0 1 2

6-2 | tmp nxtptr = 11

6-3 | at 2

6-1 | 7 6-3 | 9 dataMem@9

Step 3 6 6-0 | 3
0 1 2

Step 4 6 6-0 | 3 6-1 | 7 6-3 | 9 6-2 | 11

0 1 2 3
 0 0-0
1 0-1
1 0 11
2 5-1
6-3 INS6-2 nxt_ptr_srvr

8 1
3 6-1 5. update data 10 2
3. Read data at address
4 data_mem num-1 7 3
5 5-0 nxt_ptr 4
2 5 2. Read 1
6 6-0 0
3 6
7 6-2 -> 6-3
5 9 7 6. update nxt_ptr
4. copy to tmp
8 data_mem 1. Read 0 nxt_ptr 8
6
9 data_mem -> 6-2 nxt_ptr -> 11 9
6-2
10 data_mem 15 nxt_ptr 10
7. write back tmp
nxt_ptr 11
11 data_mem data
nxt_ptr 12
12 data_mem
nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem 4 15
15 15-0 nxt_ptr 16
Operation sequence for insertion at node
number
• Read hdptr and node_cntr mem
• Check if req_node_num < node_cntr (reqstd. Node number for insertion is smaller than
node count of that ll), else exec_error
• Fwd req_node_num to rd_ctrl and travese nxtptr mem till req_node_num –1 to get
nxtptr_value where we need to insert new data
• Read datamem at nxtptr_value and store in write_back_tmp register
• Upd req_data to that dataMem location
• Read nxtrptrMem @nxtptr_value ie nxt_nxtptr_value
• update the nxtptrMem location @nxt_nxtptr_value with nxt_avail_ptr value obtained from
nxtptr_srvr_unit
• Write back the data in 'write_back_tmp' register to the dataMem location
@nxt_nxtptr_value
• Op_done
Insertion at
head
Step 1 6 6-0 | 3 6-1 | 7 6-2 | 9

6-3 | at H nxtptr = 11

Step 2 6 6-0 | 3 6-1 | 7 6-2 | 9

Node num-> 0 1 2

6-3 | at H dataMem@11

6 -> 11
6-0 | 3 6-1 | 7 6-3 | 9
Step 3
0 1 2

Step 4 11 6-3 | 6 6-0 | 3 6-1 | 7 6-3 | 9 6-2 | 11

0 1 2 3 4
 0 0-0
1 0-1
1 0 nxt_ptr_srvr 11
2 5-1
6-3 6H
8 1
3 6-1 10 2
4 data_mem 4. update data 7 3
value@Head nxt_ptr 4
5 5-0
0 2 5
6 6-0
5. copy new 3 6
7 6-2 5 nxt_ptr 9 7
8 data_mem 6 -> 11 nxt_ptr 8
2. get nxt_ptr
9 data_mem nxt_ptr 9
15
10 data_mem nxt_ptr 10
1. rd n store hdptr in tmp nxt_ptr -> 6 11
11 data_mem -> 6-3
6 nxt_ptr 12
12 data_mem
3. update nxt_ptr nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem 4 15
15 15-0 nxt_ptr 16
Sequence for insertion at head
1. rd the hdptr n ndcntr mem @ll_num, str hdptr in hdptr_tmp

2. Send wr_req to wr_ctrl and pass req_data and hdptr_tmp to it

3. Wr_ctrl should get the nxt_avail_ptr from nxtptr_srvr as new_hdptr, write req_data to dataMem
and hdptr_tmp to nxtptrMem @location new_hdptr

4. Fwd new_hdptr to ll_mngr

5. ll_mngr should update the hdptrMem with the value new_hdptr @ll_num and update
ndcntrMem with its incremented value

6. ll_mngr will send out req to gen resp

Deletion at tail
Step 1 6 6-0 | 3 6-1 | 7 6-2 | 9

nxt_ptr_srvr

Step 2 6 6-0 | 3 6-1 | 7 6-2 | 9

Node num-> 0 1 2

nxt_ptr_srvr | 9

Step 3 6 6-0 | 3 6-1 | 7

Node num-> 0 1 2
0 0-0
1 0-1
1 0 nxt_ptr_srvr -
2 5-1
- 6DT
8 1
3 6-1 10 2
4 15-1 7 3
4.data
5 5-0 2.traverse ll 11 4 2.traverse ll
Automatically
unlinked Till tail 2 5
6 6-0 0
3 6
7 6-2 4.return
5 9 7
8 0-2 1. Rd hdptr nxtptr
12 8
6|3 3.cp nxtptr
9 data_mem nxt_ptr 9
10 5-2 15 14 10
9 nxt_ptr 11
11 data_mem
13 12
12 0-3
nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem 4 15
15 15-0 nxt_ptr 16
Sequence for deletion at tail
1. RD hdptrMem and nd_cntrMem @ll_num to get cnt, hdptr_value

2. send traverse req to rd_ctrl starting @hdptr_value till cnt-1 to get

nxtptr_value

3. CP nxtptr_value and str in tmp

4. ll_mngr will return nxtptr_value to nxtptr_srvr

5. send response
Deletion at
Head
Step 1 6 6-0 | 3 6-1 | 7 6-2 | 9

nxt_ptr_srvr

Step 2 6 6-0 | 3 6-1 | 7 6-2 | 9

Node num-> 0 1 2

nxt_ptr_srvr | 6 6-0

Step 3 3 6-1 | 7 6-2 | 9

Node num-> 0 1
0 0-0
1 0-1
1 0 nxt_ptr_srvr -
2 5-1
- 6DH
8 1
3 6-1 10 2
4 15-1 4. automatically 7 3
disconnected 11 4
5 5-0
3. copy to tmp n head 2 5
6 6-0 0
3 6
7 6-2 3 | tmp
5 9 7
8 0-2 12 8
6|3 1. read nxtPtr at head
9 data_mem nxt_ptr 9
10 5-2 15 2. return cur head to 14 10
nxtPtrSrvr nxt_ptr 11
11 data_mem
13 12
12 0-3
nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem 4 15
15 15-0 nxt_ptr 16
Sequence for deletion at head
1. rd hdptrMem n ndcntrMem @location ll_num

2. send single nxtptrMem rd request to rd_ctrl @hdptr_value and cp to

tmp

3. return hdptr_value to nxtptr_srvr

4. cp value in tmp to hdptrMem @ll_num

Deletion a node
num
Step 1 6 6-0 | 3 6-1 | 7 6-2 | 9 6-3 | 12 6-4 | 5

Node num-> 0 1 2 3 4

nxt_ptr_srvr
Memlocation -> 6 3 7 9 12

Step 2 6 6-0 | 3 6-1 | 7 6-2 | 9 6-3 | 12 6-4 | 5

Node num-> 0 1 2 3 4

nxt_ptr_srvr |7 6-2
Memlocation -> 6 3 9 12
Step 3 6 6-0 | 3 6-1 | 9 6-3 | 12 6-4 | 5
Node num-> 0 1 2 3
0 0-0
1 0-1
1 0 nxt_ptr_srvr -
2 5-1
- 6D1
8 1
3 6-1 6. Automatically 10 2
disconnected 2. rd nxt -> cnt 1 = num
4 15-1 7 3
3. cp nxtPtr to tmp
5 5-0 11 4
2 5
6 6-0 0
3 6
7 6-2 7 | tmp
5 5. upd nxtPtr from tmp 9 7 4. return nxtPtr
8 0-2 12 8
6
9 data_mem 1. rd Hd -> cnt 0 nxt_ptr 9
10 5-2 15 14 10
nxt_ptr 11
11 data_mem
13 12
12 0-3
nxt_ptr 13
13 data_mem nxt_ptr 14
14 data_mem 4 15
15 15-0 nxt_ptr 16
Sequence to delete middle node
1. rd hdptr and nd_cntr Mems @ location ll_num
2. send rd req to rd_ctrl to travese nxtptr Mem till node_num - 1
3. while traversing, cp the prev_address and current addr
4. cp to tmp and return the nxtptr value at node_num – 1 to
nxtptr_srvr
4. rd the nxtptr Mem @location: tmp and send it to ll_mngr
5. send a nxtptr Mem only write req to wr_ctrl with data: tmp and
@location: prev_address
6. upd nodeCntr and send resp once wr_ctrl is done
Instruction
Set
Opcode

Main Operation specifier Data

Node number (optnl) Data value (for insert/update)
ROM DMA ENGINE
 0 05 1
Example
1 07 2 Hd| 0 05| 1 07 | 2 01 | 3
0| 0 1| 1 2| 2
2 01 3
3
4
5 Hd| 0 05| 0->2 01 | 3
0| 0 1| 2
6
7

0 8 07 | 2
1 9 1| 1
2 a
b Ret 1
3 0
c
d
e
f