Design

Methodology

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 The Design Productivity Challenge
10,000,000 100,000,000

Productivity (Trans./Staff-Month)
Logic Transistors per Chip (K)

1,000,000 10,000,000

100,000 58%/Yr. compound 1,000,000

Complexity growth rate
10,000 100,000

1,000 10,000

100 1,000

10 Productivity growth rate 100

21%/Yr. compound

1997
1981

1985

1993

2001

2005

2009
1989

A growing gap between design complexity and design productivity

Source: ITRS’97

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 The Custom Approach
Intel 4004

© Digital Integrated Circuits2nd and F. BrewerCourtesy

2003 Intel Design Methodologies
Transition to Automation and Regular Structures

Intel 4004 (‘71)

Intel 8080 Intel 8085

Intel 80286 Intel 80486

© Digital Integrated Circuits2nd and F. BrewerCourtesy
2003 Intel Design Methodologies
 Automating Design
 Exploitation By Algorithms
 Regular Structures
 Logic Synthesis
 Regularization of Connection
 Floorplanning (Localization of function)
 System Level Performance/Power/Cost
 Allocation of Physical Resources
 Communication/Interconnect
 Hierarchy based on Sensitivity to Latency
 Wires to Link Protocols

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 A System-on-a-Chip: Example

Courtesy: Philips

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 Design Methodology

• Design process traverses iteratively between three abstractions:

behavior, structure, and geometry
• More and more automation for each of these steps

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 Floorplanning

A Protocol Processor for Wireless

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies
 Implementation Choices

Digital Circuit Implementation Approaches

Custom Semicustom

Cell-based Array-based

Standard Cells Pre-diffused Pre-wired

Macro Cells
Compiled Cells (Gate Arrays) (FPGA's)

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 Impact of Implementation Choices

Domain-specific processor
100-1000
Energy Efficiency (in MOPS/mW)

Embedded microprocessor
10-100

(e.g. DSP)
Configurable/Parameterizable
Hardwired custom

1-10

0.1-1

None Somewhat Fully Flexibility

flexible flexible (or application scope)

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 Implementation Strategies
 PLA
 Technology confined in cell macros (tiling)
 Cell based logic
 Technology confined to cells (area)
 Both 1-d and 2-d solutions
 Transistor Arrays (Gate arrays)
 Technology confined to layers (Below M1
fixed)

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 PLA: Programmable Logic Array
Product terms

x0 x1
x2
AND OR
plane plane

f0 f1

x0 x1 x2

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 Two-Level Logic
Every logic function can be
expressed in sum-of-products
format (AND-OR)

minterm

Inverting format (NOR-

NOR) more effective

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 PLA Layout – Exploiting Regularity
And-Plane Or-Plane
V DD  GND

x0 x0 x1 x1 x2 x2 f0 f1
Pull-up devices Pull-up devices

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 Breathing Some New Life in PLAs
River PLAs
 A cascade of multiple-output PLAs.
 Adjacent PLAs are connected via river routing.
PRE-CHARGE

BUFFER
B U FFER PR E-C H AR G E
CHARGE

BUFFER
PRE-

B U FFER PR E-C H AR G E
PRE-CHARGE

BUFFER

B U FFER PR E-C H AR G E

• No placement and routing needed.

CHARGE

BUFFER
PRE-

B U FFER PR E-C H AR G E
• Output buffers and the input buffers
of the next stage are shared.

© Digital Integrated Circuits2nd and F. BrewerCourtesy

2003 B. Brayton Design Methodologies
 delay
Experimental Results 1.4

Area:
RPLAs (2 layers) 1.23
SCs (3 layers) - 1.00, 1
NPLAs (4 layers) 1.31
Delay
RPLAs 1.04
SCs 1.00
0.6
NPLAs 1.09
Synthesis time: for RPLA , synthesis time equals design time;
SCs and NPLAs still need P&R.
Also: RPLAs are regular and predictable
0.2
0 2 4 6 area

Layout of C2670 SC NPLA RPLA

Standard cell, Standard cell, Network of PLAs, River PLA,

2 layers channel routing 3 layers OTC 4 layers OTC 2 layers no additional routing

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 2-d Cell Based: “Hard” Modules

25632 (or 8192 bit) SRAM

Generated by hard-macro module generator

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 1-d Cell-based Design (standard cells)
Feedthrough cell Logic cell

Routing
channel

Rows of
cells
Functional Routing channel
module requirements are
reduced by presence
(RAM, of more interconnect
multiplier, layers
)

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 Standard Cell — Example

[Brodersen92]

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 Standard Cell – The New Generation

Cell-structure
hidden under
interconnect layers

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 Standard Cell - Example

3-input NAND cell

(from ST Microelectronics):
C = Load capacitance
T = input rise/fall time

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 “Soft” MacroModules

Synopsys
© Digital Integrated Circuits2nd and F. Brewer 2003 DesignCompiler Design Methodologies
 The “Design Closure” Problem

Iterative Removal of Timing Violations (white lines)

Courtesy
© Digital Integrated Circuits2nd and F. Brewer 2003 Synopsys Design Methodologies
 Gate Array — Sea-of-gates

polysilicon

VD D

metal
rows of Uncommited
uncommitted possible
cells GND contact Cell

In1 In2 In3 In4

routing
channel Committed
Cell
(4-input NOR)
Out

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 Sea-of-gate Primitive Cells
Oxide-isolation

PMOS

PMOS

NMOS

NMOS
NMOS

Using oxide-isolation Using gate-isolation

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 Sea-of-gates

Random Logic

Memory
Subsystem

LSI Logic LEA300K

(0.6 m CMOS)

© Digital Integrated Circuits2nd and F. Brewer 2003 LSI Logic

Courtesy Design Methodologies
 The return of gate arrays?
Via programmable gate arra
(VPGA)

Via-programmable cross-point

metal-5 metal-6

programmable via

Exploits regularity of interconnect

[Pileggi02]
© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies
 Pre-wired Arrays:
Classification of prewired arrays (or field-programmable devices):
 Based on Programming Technique
 Fuse-based (program-once)
 Non-volatile EPROM based
 RAM based
 Programmable Logic Style
 Array-Based
 Look-up Table
 Programmable Interconnect Style
 Channel-routing
 Mesh networks

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 Fuse-Based FPGA
antifuse polysilicon ONO dielectric

n+ antifuse diffusion

2

Open by default, closed by applying current pulse

© Digital Integrated Circuits2nd and F. Brewer 2003

From Smith’97 Design Methodologies
 Array-Based Programmable Logic
I5 I4 I3 I2 I1 I0 Programmable
OR array I3 I2 I1 I0 Programmable
OR array I5 I4 I3 I2 I1 I0 Fixed OR array

Programmable AND array Fixed AND array Programmable AND array

O 3O 2O 1O 0 O3O2O1O0 O 3O 2O 1 O 0

PLA (flexible – sizing) PROM (dense) PAL (uniform load)

Indicates programmable connection
Indicates fixed connection

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 Programming a PROM
1 X2 X1 X0

: programmed node
NA NA f 1 f 0

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 2-input mux
as programmable logic block
Configuration
A B S F=
0 0 0 0
0 X 1 X
A 0 0 Y 1 Y
F 0 Y X XY
X 0 Y XY
B 1
Y 0 X XY
Y 1 X X +Y
1 0 X X
S
1 0 Y Y
1 1 1 1

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 Logic Cell of Actel Fuse-Based FPGA

B 1
SA Y
1
C

D 1
SB
S0
S1

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 LUT-Based Logic Cell
4
C1....C4

H1 H2 H0 EC

D4 S/R Bypass
Logic Din
control
D3 YQ
function F’
G’
D SD Q
D2 F H’

D1
Logic EC RD
function G’
H’
H 1 Y
F4
S/R Bypass
F3 Logic control XQ
Din
function F’ D SD Q
F2 G’
G H’
F1
EC RD
clock
H’ 1 X
F’
Multiplexer Controlled
by Configuration Program
Xilinx 4000 Series

© Digital Integrated Circuits2nd and F. BrewerCourtesy

2003 Xilinx Design Methodologies
 Array-Based Programmable Wiring
Interconnect
Point
M

Programmed interconnection Input/output pin

Cell

Horizontal
tracks

Vertical tracks

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 Mesh-based Interconnect Network
Switch Box

Connect Box

Interconnect
Point

© Digital Integrated Circuits2nd and F.Courtesy

Brewer 2003
Dehon and Wawrzyniek Design Methodologies
 Transistor Implementation of Mesh

© Digital Integrated Circuits2nd and F.Courtesy

Brewer 2003
Dehon and Wawrzyniek Design Methodologies
 Hierarchical Mesh Network

Use overlayed mesh

to support longer connections

Reduced fanout and reduced

resistance

© Digital Integrated Circuits2nd and F.Courtesy

Brewer 2003
Dehon and Wawrzyniek Design Methodologies
 Altera MAX

© Digital Integrated Circuits2nd and F. Brewer 2003

From Smith97 Design Methodologies
 Altera MAX Interconnect Architecture
column channel row channel

t PIA

LAB1 LAB2

LAB

PIA

t PIA
LAB6

Array-based Mesh-based
(MAX 3000-7000) (MAX 9000)

© Digital Integrated Circuits2nd and F. BrewerCourtesy

2003 Altera Design Methodologies
 Field-Programmable Gate Arrays
Fuse-based
I/O Buffers

P rogram/ Tes t/Diag nostics

Vertical ro utes

Standard-cell like
floorplan
I/O Buffers

I/O Buffers
Rows o f logic m odule s
Routing c hannels

I/O Buffers

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 Xilinx 4000 Interconnect Architecture

12 Quad

8 Single

4 Double

3 Long

Direct
CLB 2 Connect

3 Long
12 4 4 8 4 8 4 2

Quad Long Global Long Double Single Global Carry Direct

Clock Clock Chain Connect

© Digital Integrated Circuits2nd and F. BrewerCourtesy

2003 Xilinx Design Methodologies
 RAM-based FPGA

Xilinx XC4000ex

© Digital Integrated Circuits2nd and F. BrewerCourtesy

2003 Xilinx Design Methodologies
 Design at a crossroad
System-on-a-Chip

500 k Gates FPGA  Embedded applications:

Analog
Multi-
Spectral
RAM + 1 Gbit DRAM cost, performance, and
Imager Preprocessing energy are the issues!
 DSP and control intensive
64 SIMD Processor C
Array + SRAM system  Mixed-mode
+2 Gbit  Software design is crucial
Image Conditioning DRAM
100 GOPS Recog-
nition

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 Addressing the Design Complexity Issue
Architecture Reuse

Reuse comes in generations

Generation Reuse element Status
1st Standard cells Well established
2nd IP blocks Established- marginal
3rd Architecture Need for Standards
4th IC Marketing Hype
5th Software Current Practice

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies

 Heterogeneous Programmable Platforms
FPGA Fabric

Embedded memories
Embedded PowerPc

Hardwired multipliers

Xilinx Vertex-II Pro

High-speed I/O
Courtesy: Xilinx
© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies
 Summary
 Design Choice forced by System Tradeoffs
 Deep Sub-micron Challenges
Regularity (Design flexibility at smallest scales)
Power consumption!
Interconnection Parasitics
Nanoscopic Devices/Modules
New circuit solutions are bound to emerge
 Who can afford design in the years to come?

© Digital Integrated Circuits2nd and F. Brewer 2003 Design Methodologies