ELE4204: Computer Engineering II

Chapter 2
Shift Registers
Dr. N.B. Kadandani
PhD (Newcastle upon Tyne), M.Eng., B.Eng. (BUK), ITEC (Chennai)
MNSE, RE (COREN), MIEEE
Department of Electrical Engineering, Bayero University, Kano, Nigeria
[email protected]

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 Outline of the Chapter

• Introduction
• Shift Register Operations
• Types of Shift Register Data I/Os
• Bidirectional Shift Registers
• Shift Register Counters
• Shift Register Applications
• Summary/Conclusion
• Key Terms Used in the Chapter

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 Chapter Objectives
• Identify the basic forms of data movement in shift registers
• Explain how serial in/serial out, serial in/parallel out, parallel
in/serial out, and parallel in/parallel out shift registers operate
• Describe how a bidirectional shift register operates
• Determine the sequence of a Johnson counter
• Set up a ring counter to produce a specified sequence
• Construct a ring counter from a shift register
• Use a shift register as a time-delay device
• Use a shift register to implement a serial-to-parallel data
converter
• Implement a basic shift-register-controlled keyboard encoder
• Use shift registers in a system application
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 Introduction
• Shift registers are a type of sequential logic circuit used primarily for the
storage of digital data and typically do not possess a characteristic internal
sequence of states.
• There are exceptions, however, and these are covered under shift register
counters.
• In this chapter, the basic types of shift registers are studied and several
applications are presented.
• Shift registers consist of arrangements of flip-flops and are important in
applications involving the storage and transfer of data in a digital system.
• A register has no specified sequence of states, except in certain very
specialized applications.
• A register, in general, is used solely for storing and shifting data (1s and 0s)
entered into it from an external source and typically possesses no
characteristic internal sequence of states.
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 Shift Register Operations
• A register is a digital circuit with two basic
functions: data storage and data movement.
• The storage capability of a register makes it
an important type of memory device.
• Figure 2–1 illustrates the concept of storing a
1 or a 0 in a D flip-flop. FIGURE 2–1: (a)
• A 1 is applied to the data input as shown, and
a clock pulse is applied that stores the 1 by
setting the flip-flop.
• When the 1 on the input is removed, the flip-
flop remains in the SET state, thereby storing
the 1.
• A similar procedure applies to the storage of a
FIGURE 2–1: (b)
0 by resetting the flip-flop, as also illustrated
in Figure 2–1. 5
FIGURE 2–1: The flip-flop as a storage element
 Shift Register Operations
• The storage capacity of a register is the total number of bits (1s and 0s) of digital data it
can retain.
• Each stage (flip-flop) in a shift register represents one bit of storage capacity; therefore,
the number of stages in a register determines its storage capacity.
• The shift capability of a register permits the movement of data from stage to stage within
the register or into or out of the register upon application of clock pulses.
• Figure 2–2 illustrates the types of data movement in shift registers. The block represents
any arbitrary 4-bit register, and the arrows indicate the direction of data movement.

FIGURE 2–2: Basic data movement in shift registers. (Four bits are used for illustration.6
The bits move in the direction of the arrows.)
 The Storage Function of a Shift Register
• A register is formed by combining several flip-flops so that groups of bits can be stored. For
example, an 8-bit register is constructed from eight flip-flops.
• In addition to storing bits, registers can be used to shift the bits from one position to another
within the register or out of the register to another circuit; therefore, these devices are known as
shift registers.
• The two basic types of shift registers are serial and parallel. The bits are stored in a serial shift
register one at a time, as illustrated in Figure 2–3.

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FIGURE 2–3: Example of the operation of a 4-bit serial shift register. Each block represents one storage “cell” or flip-flop.
 The Storage Function of a Shift Register
• A good analogy to the serial shift register is loading passengers onto a bus single file
through the door. They also exit the bus single file.
• The bits are stored in a parallel register simultaneously from parallel lines, as shown in
Figure 2–4.
• For this case, a good analogy is loading and unloading passengers on a roller coaster
where they enter all of the cars in parallel and exit in parallel.

FIGURE 2–4: Example of the operation of a 4-bit

parallel shift register.

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FIGURE 2–3: Example of the operation of a 4-bit serial shift register. Each block represents one storage “cell” or flip-flop.
 Types of Shift Register Data I/Os
• In this section, four types of shift registers based on data
input and output (inputs/outputs) are discussed:
• Serial in/serial out
• Serial in/parallel out
• Parallel in/serial out
• Parallel in/parallel out

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 Serial In/Serial Out Shift Registers
• The serial in/serial out shift register accepts data
serially—that is, one bit at a time on a single line.
• It produces the stored information on its output also in
serial form.
• Let’s first look at the serial entry of data into a typical
shift register.
• Figure 2–5 shows a 4-bit device implemented with D FIGURE 2–5: Serial in/serial out shift register.
flip-flops.
• With four stages, this register can store up to four bits
of data. TABLE 2–1: Shifting a 4-bit code into the
shift register in Figure 2–5. Data bits are
• Table 2–1 shows the entry of the four bits 1010 into the indicated by a beige screen.
register in Figure 2–5, beginning with the least
significant bit. The register is initially clear.
• The 0 is put onto the data input line, making D = 0 for
FF0. When the first clock pulse is applied, FF0 is reset,
thus storing the 0
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 Serial In/Serial Out Shift Registers
• Next the second bit, which is a 1, is applied to the data input,
making D = 1 for FF0 and D = 0 for FF1 because the D input
of FF1 is connected to the output.
• When the second clock pulse occurs, the 1 on the data input
is shifted into FF0, causing FF0 to set; and the 0 that was in
FF0 is shifted into FF1.
• The third bit, a 0, is now put onto the data-input line, and a
clock pulse is applied. FIGURE 2–5: Serial in/serial out shift register.
• The 0 is entered into FF0, the 1 stored in FF0 is shifted into
FF1, and the 0 stored in FF1 is shifted into FF2.
• The last bit, a 1, is now applied to the data input, and a clock TABLE 2–1: Shifting a 4-bit code into the
pulse is applied. shift register in Figure 2–3. Data bits are
indicated by a beige screen.
• This time the 1 is entered into FF0, the 0 stored in FF0 is
shifted into FF1, the 1 stored in FF1 is shifted into FF2, and
the 0 stored in FF2 is shifted into FF3.
• This completes the serial entry of the four bits into the shift
register, where they can be stored for any length of time as
long as the flip-flops have DC power. 11
 Serial In/Serial Out Shift Registers
• If you want to get the data out of the register, the bits must be shifted out
serially to the output, as Table 2–2 illustrates.
• After CLK4 in the data-entry operation just described, the LSB, 0, appears on
the output.
• When clock pulse CLK5 is applied, the second bit appears on the output.
Clock pulse CLK6 shifts the third bit to the output, and CLK7 shifts the fourth
bit to the output.
• While the original four bits are being shifted out, more bits can be shifted in.
All zeros are shown being shifted in, after CLK8.
TABLE 2–2: Shifting a 4-bit code out of the shift register in
Figure 2–3. Data bits are indicated by a beige screen.

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FIGURE 2–5: Serial in/serial out shift register.
 Serial In/Serial Out Shift Registers
Example 2-1: Show the states of the
5-bit register in Figure 2–6(a) for the
specified data input and clock
waveforms. Assume that the register
is initially cleared (all 0s).
Solution:
• The first data bit (1) is entered into
the register on the first clock pulse
and then shifted from left to right as
the remaining bits are entered and
shifted as shown in Table 2–3.
• The register contains = 11010 after
five clock pulses. See Figure 2–6(b).

FIGURE 2–6 13
 Serial In/Serial Out Shift Registers
TABLE 2–3: Solution to Example 2-1

FIGURE 2–6 14
 Serial In/Parallel Out Shift Registers
• Data bits are entered serially (least-significant bit first) into a serial in/parallel out
shift register in the same manner as in serial in/serial out registers.
• The difference is the way in which the data bits are taken out of the register; in the
parallel output register, the output of each stage is available.
• Once the data are stored, each bit appears on its respective output line, and all bits
are available simultaneously, rather than on a bit-by-bit basis as with the serial
output.
• Figure 2-7(a) shows a 4-bit serial in/parallel out shift register while Figure 2-7(b)
shows its logic block symbol. The “SRG 4” designation indicates a shift register
(SRG) with a 4-bit capacity.

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FIGURE 2–7: A serial in/parallel out shift register
 Serial In/Parallel Out Shift Registers
Example 2-2:
Show the states of the 4-bit register (SRG 4) for the data input and clock
waveforms in Figure 2-8(a). The register initially contains all 1s.
Solution:
The register contains 0110 after four clock pulses. See Figure 2-8(b).

FIGURE 2–8 16
 Parallel In/Serial Out Shift Registers
• For a register with parallel data inputs, the bits are
entered simultaneously into their respective stages on
parallel lines rather than on a bit-by-bit basis on one
line as with serial data inputs.
• The serial output is the same as in serial in/serial out
shift registers, once the data are completely stored in
the register.
• Figure 2-9 illustrates a 4-bit parallel in/serial out shift
register and a typical logic symbol.

TABLE 2–4: Truth table TABLE 2–5: Truth table

for a 2-input AND gate. for a 2-input OR gate.

FIGURE 2–9: A 4-bit parallel in/serial out shift17register.

 Parallel In/Serial Out Shift Registers
• There are four data-input lines, , , , and , and a SHIFT/
input, which allows four bits of data to load in parallel
into the register.
• When SHIFT/ is LOW, gates through are enabled,
allowing each data bit to be applied to the D input of
its respective flip-flop.
• When a clock pulse is applied, the flip-flops with D = 1
will set and those with D = 0 will reset, thereby storing
all four bits simultaneously.

TABLE 2–4: Truth table TABLE 2–5: Truth table

for a 2-input AND gate. for a 2-input OR gate.

FIGURE 2–9: A 4-bit parallel in/serial out shift18register.

 Parallel In/Serial Out Shift Registers
• When SHIFT/ is HIGH, gates through are
disabled and gates through are enabled,
allowing the data bits to shift right from one
stage to the next.
• The OR gates allow either the normal shifting
operation or the parallel data-entry operation,
depending on which AND gates are enabled by
the level on the SHIFT/ input.
• Notice that FF0 has a single AND to disable
the parallel input, . It does not require an
AND/OR arrangement because there is no
serial data in.
TABLE 2–4: Truth table TABLE 2–5: Truth table
for a 2-input AND gate. for a 2-input OR gate.

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FIGURE 2–9: A 4-bit parallel in/serial out shift register.
 Parallel In/Serial Out Shift Registers
Example 2-3: Show the data-output waveform for
a 4-bit register with the parallel input data and the
clock and SHIFT/ waveforms given in Figure 2–
10(a).
Solution:
• On clock pulse 1, the parallel data ( = 1010) are
loaded into the register, making a 0;
• On clock pulse 2 the 1 from is shifted onto ;
• On clock pulse 3 the 0 from is shifted onto ;
• On clock pulse 4 the last data bit (1) from is
shifted onto ;
• On clock pulse 5, all data bits have been shifted
out, and only 1s remain in the register (assuming FIGURE 2–10
the input remains a 1).
• See Figure 2-10(b).
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 Parallel In/Parallel Out Shift Registers
• Parallel entry and parallel output of data have been discussed.
• The parallel in/parallel out register employs both methods.
• Immediately following the simultaneous entry of all data bits, the bits
appear on the parallel outputs.
• Figure 2-11 shows a parallel in/parallel out shift register.

FIGURE 2–11: A parallel in/parallel out register 21

 Bidirectional Shift Registers
• A bidirectional shift register is one in which the data can be shifted either left or right.
• It can be implemented by using gating logic that enables the transfer of a data bit from one stage to
the next stage to the right or to the left, depending on the level of a control line.
• A 4-bit bidirectional shift register is shown in Figure 2-12.
• A HIGH on the RIGHT/ control input allows data bits inside the register to be shifted to the right, and a
LOW enables data bits inside the register to be shifted to the left. An examination of the gating logic
will make the operation apparent.

TABLE 2–4: Truth table TABLE 2–5: Truth table

for a 2-input AND gate. for a 2-input OR gate.

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FIGURE 2–12: Four-bit bidirectional shift register
 Bidirectional Shift Registers
• When the RIGHT/ control input is HIGH, gates through are enabled, and the state of the Q output of
each flip-flop is passed through to the D input of the following flip-flop.
• When a clock pulse occurs, the data bits are shifted one place to the right.
• When the RIGHT/ control input is LOW, gates through are enabled, and the Q output of each flip-flop
is passed through to the D input of the preceding flip-flop.
• When a clock pulse occurs, the data bits are then shifted one place to the left.

TABLE 2–4: Truth table TABLE 2–5: Truth table

for a 2-input AND gate. for a 2-input OR gate.

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FIGURE 2–12: Four-bit bidirectional shift register
 Shift Register Counters
• A shift register counter is basically a shift register with the serial
output connected back to the serial input to produce special
sequences.
• These devices are often classified as counters because they exhibit
a specified sequence of states.
• Two of the most common types of shift register counters, are
introduced in this section.
• Namely:
• The Johnson counter, and
• The ring counter,

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 The Johnson Counter
• In a Johnson counter the complement of the
TABLE 2–6: Four-bit Johnson sequence.
output of the last flip-flop is connected back to
the D input of the first flip-flop (it can be
implemented with other types of flip-flops as
well).
• If the counter starts at 0, this feedback
arrangement produces a characteristic
sequence of states, as shown in Table 2–6 for
a 4-bit device and in Table 2–7 for a 5-bit TABLE 2–7: Five-bit Johnson sequence.
device.
• Notice that the 4-bit sequence has a total of
eight states, or bit patterns, and that the 5-bit
sequence has a total of ten states.
• In general, a Johnson counter will produce a
modulus of 2n, where n is the number of
stages in the counter. 25
 The Johnson Counter
• The implementations of the 4-stage and 5-
stage Johnson counters are shown in Figure
2-13.
• The implementation of a Johnson counter is
very straightforward and is the same
regardless of the number of stages.
• The Q output of each stage is connected to
the D input of the next stage (assuming that D
flip-flops are used).
• The single exception is that the output of the
last stage is connected back to the D input of
the first stage.
• As the sequences in Table 2-7 and 2-8 show, if FIGURE 2-13: Four-bit and 5-bit
the counter starts at 0, it will “fill up” with 1s Johnson counters.
from left to right, and then it will “fill up” with 0s
again. 26
 The Johnson Counter
• Diagrams of the timing operations of the 4-bit and 5-bit counters are shown in Figures
2-14 and 2-15, respectively. TABLE 2–6: Four-bit Johnson sequence.

FIGURE 2-14: Timing sequence for a 4-bit Johnson counter. TABLE 2–7: Five-bit Johnson sequence.

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FIGURE 2-15: Timing sequence for a 5-bit Johnson counter.
 The Ring Counter
• A ring counter utilizes one flip-flop for each state in its sequence.
• It has the advantage that decoding gates are not required. In the case of a 10-bit
ring counter, there is a unique output for each decimal digit.
• A logic diagram for a 10-bit ring counter is shown in Figure 2-16. The sequence for
this ring counter is given in Table 2–8.
• Initially, a 1 is preset into the first flip-flop, and the rest of the flip-flops are cleared.
• Notice that the interstage connections are the same as those for a Johnson
counter, except that Q rather than is fed back from the last stage.

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FIGURE 2-16: A 10-bit ring counter.
 The Ring Counter
• The ten outputs of the counter TABLE 2-8: Ten-bit ring counter sequence.
indicate directly the decimal count of
the clock pulse.
• For instance, a 1 on represents a
zero, a 1 on represents a one, a 1 on
represents a two, a 1 on represents a
three, and so on.
• You should verify for yourself that the
1 is always retained in the counter
and simply shifted “around the ring,”
advancing one stage for each clock
pulse.
• Modified sequences can be achieved
by having more than a single 1 in the
counter. FIGURE 2-16: A 10-bit ring counter.
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 Shift Register Applications
• Time Delay
• A serial in/serial out shift register can be used to provide a time delay from input to output
that is a function of both the number of stages (n) in the register and the clock frequency.
• Serial-to-Parallel Data Converter
• Serial data transmission from one digital system to another is commonly used to reduce
the number of wires in the transmission line. For example, eight bits can be sent serially
over one wire, but it takes eight wires to send the same data in parallel.
• Universal Asynchronous Receiver Transmitter (UART)
• As mentioned, computers and microprocessor-based systems often send and receive
data in a parallel format. Frequently, these systems must communicate with external
devices that send and/or receive serial data. An interfacing device used to accomplish
these conversions is the UART (Universal Asynchronous Receiver Transmitter). A UART
includes both serial-to-parallel and parallel-to-serial conversion.
• Keyboard Encoder
• The keyboard encoder is a good example of the application of a shift register used as a
ring counter in conjunction with other devices. 30
 Summary/Conclusion
• The basic types of data movement in shift registers are:
• Serial in/shift right/serial out
• Serial in/shift left/serial out
• Parallel in/serial out
• Serial in/parallel out
• Parallel in/parallel out
• Rotate right
• Rotate left
• Shift register counters are shift registers with feedback that exhibit special
sequences. Examples are the Johnson counter
• The Johnson counter has 2n states in its sequence, where n is the number
of stages.
• The ring counter has n states in its sequence.
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 Key Terms Used in the Chapter
• Bidirectional: Having two directions. In a bidirectional
shift register, the stored data can be shifted right or left.
• Load: To enter data into a shift register.
• Register: One or more flip-flops used to store and shift
data.
• Stage: One storage element in a register.

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*

Questions
???
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