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Intro To Pentium Microprocessor

Explained about pentium microprocessors

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59 views21 pages

Intro To Pentium Microprocessor

Explained about pentium microprocessors

Uploaded by

gamingbuddy24
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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INTRODUCTION TO THE

PENTIUM
MICROPROCESSOR
Presented by Rohit, Sahil and
Sambhav
01. The Pentium microprocessor is
packaged in a 237-pin PGA (pin
grid array).

Pin-out of the
pentium 02.
There are two versions: the
full Pentium and the P24T

microprocessor version called the Pentium


OverDrive.
The P24T version is designed to be
compatible with 80486 machines and
03. features a 32-bit data bus. It has a
larger physical footprint due to 64
data bus connections compared to
the 32 in earlier 80486
microprocessors.
01.
Early versions of the Pentium
require a single +5.0 V power
supply.

Power Supply There are two versions: the


02.
Requirements full Pentium and the P24T
version called the Pentium
OverDrive.

Power dissipation for these


03. microprocessors is 13 W for the
66 MHz version and 11.9 W for
the 60 MHz version.
The power dissipation of the
Pentium microprocessors is
01. significant, necessitating

Power Dissipation
proper cooling.

and Cooling
Heat sinks with considerable
02. airflow are required to keep
the Pentium cool.
The Pentium microprocessor
contains multiple VCC (+5.0 V
01. or +3.3 V) and VSS (ground)

Voltage and connections for proper


operation.

Ground
Connections
Proper connections of these
02. voltage and ground pins are
essential.
Each Pentium output pin can
provide 4.0 mA of current at a
01. logic 0 level and 2.0 mA at a

Output and Input


logic 1 level.

Characteristics
Input pins have a small load,
02. requiring only 15 μA of
current.
No Connection (N/C) Drive Current
Pins Increase
Some pins are labeled The Pentium microprocessor
provides increased drive
N/C (no connection)
current compared to earlier
and must not be microprocessors like 8086,
connected. 8088, and 80286.

Bus
Buffers
In some systems,
except the smallest,
bus buffers may be
required due to the
current levels.
Address Bus and Control
Pins

• A20: Input for addressing in real mode, signaling Pentium to perform


address wraparound.
• A31–A3: Address bus connections for addressing 512K × 64 memory
locations.
• ADS: Address Data Strobe, active when Pentium issues a valid memory
or I/O address.
• APCHK: Address Parity Check, checks even parity for memory address
on Pentium-initiated transfers.
Bus Control and Timing
Pins:

• BE7–BE0: Bus Enable connections, encode A0, A1, and A2 to select bytes
in a 64-bit-wide memory location.
• MIO: Memory Input/Output, input for holding the address and AP signals
for the next clock.
• AHOLD: Address Hold, input causing Pentium to hold address and AP
signals for the next clock.
Cache and Clock
Pins

• CACHE: Cache output, indicating the current cycle can cache data.

• CLK: Clock input driven by a clock signal at the operating frequency of


the Pentium.
Data Bus and Control
Pins

• D63–D0: Data bus connections for transferring byte, word, doubleword,


and quadword data.

• DC: Data/Control, indicates whether data bus contains data for/from


memory or I/O.
Error Handling and System Control
Pins

• FERR: Floating-Point Error, indicates an error in the internal


coprocessor
.
• FLUSH: Flush Cache, input causing the cache to flush write-back lines
and invalidate internal caches.

• FRCMC: Functional Redundancy Check, sampled during reset to


configure Pentium in master or checker mode.
Interrupt and Control
Pins

• INTR: Interrupt Request, used by external circuitry to request an


interrupt.

• RESET: Reset initializes the Pentium, causing it to begin executing


software at memory location FFFFFFF0H.
The Memory
System
Address Miscellaneous PinsBus and
Control Pins

• LOCK: Becomes logic 0 when an instruction is prefixed with the LOCK


prefix (used during DMA accesses).
• Memory/IO: Selects memory device (logic 1) or I/O device (logic 0).
• NMI: Non-Maskable Interrupt, requests a non-maskable interrupt.
• PCD: Page Cache Disable, shows the state of internal page caching.
• PRDY: Probe Ready, indicates that the probe mode has been entered
for debugging.
• PWT: Page Write-Through, shows the state of the PWT bit in CR3, used
with Intel Debugging Port.
Memory Size and
Organization:

• The Pentium memory system is 4 GB (gigabytes) in size, similar to the


80386DX and 80486 microprocessors.

• Memory is organized in eight banks, and each bank contains 512 MB


(megabytes) of data.

• The physical memory system is divided into eight banks, and each
bank stores byte-wide data with a parity bit.
Data Bus
Width

• The Pentium uses a 64-bit data bus to address memory. This is a change
from the 32-bit data bus used in earlier microprocessors like the 80486.

• The 64-bit-wide memory is particularly significant for handling double-


precision
Parity Generation and Checking

• Similar to the 80486, the Pentium employs internal parity generation


and checking logic for the memory system's data bus information.

• Parity is generated and checked for byte-wide data, and the system uses
eight separate write strobes for writing to the memory system.
Memory Selection

• Memory selection is achieved using bank enable signals (BE7–BE0).

• These separate memory banks enable the Pentium to access any single
byte, word, doubleword, or quadword with one memory transfer cycle.
Throughput Improvement

• The 64-bit-wide data bus allows the Pentium to retrieve double-precision


floating-point data with one read cycle, compared to two read cycles in the
80486.

• This results in the Pentium operating at a higher throughput than the


80486
Address Bus Parity
Checking

• A new feature in the Pentium is the capability to check and generate parity for
the address bus (A31–A5) during certain operations.

• The AP pin provides the system with parity information, and APCHK indicates a
bad parity check for the address bus.

• The Pentium takes no action when an address parity error is detected; the
system must assess the error and take appropriate action, such as generating an
interrupt.

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