Basic Logic Design With Verilog HDL:: Gate-Level Design On Combinational Circuits
Basic Logic Design With Verilog HDL:: Gate-Level Design On Combinational Circuits
Basic Logic Design With Verilog HDL:: Gate-Level Design On Combinational Circuits
Lecture note
by by by by by by
Chen-han Tsai Chih-hao Chao Xin-Yu Shi Bo-Yuan Peng Cheng-Zhou Zhan Bo-Yuan Peng
Outline
Introduction to Verilog HDL Syntax in Verilog HDL Gate-Level Modeling Test-Bench Compilation and Simulation Tools
Outline
Introduction to Verilog HDL Syntax in Verilog HDL Gate-Level Modeling Test-Bench Compilation and Simulation Tools
Cost Low
High
Verilog
Gate Level Simulation
Logic Synthesizer
Gate Level Code
Tape Out
Low
High
Chip
sel 0 out 1
sel 0 0 0 0 1 1 1 1
in1 0 0 1 1 0 0 1 1
in2 0 1 0 1 0 1 0 1
out 0 0 1 1 0 1 0 1
in1 in2
iv_sel
a1 a2
a1_o
o 1
out
a2_o
sel
iv_sel
Gate Level: you see only netlist (gates and wires) in the code.
Outline
Introduction to Verilog HDL Syntax in Verilog HDL Gate-Level Modeling Test-Bench Compilation and Simulation Tools
port/wire declaration
Module
Basic building block in Verilog Module
1. Created by declaration (cant be nested) 2. Used by instantiation
Interface is defined by ports May contain instances of other modules All modules run concurrently
Module Instantiation
Adder
instance example
Adder
Adder
Adder_tree
Instances
A module provides a template from which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters and I/O interface.
Format
module m_Name( IO list ); ... endmodule m_Name ins_name ( port connection list ); ins_name.member_signal
Instantiation
Member
Hierachy
instance.sub_instance.me mber_signal
object.sub_object.member_ data
Port Connection
Logic System
Four values: 0, 1, x/X, z/Z (not case sensitive)
The logic value x denotes an unknown (ambiguous) value The logic value z denotes a highimpedance value (High-Z value)
a b a
0 1 x
0
1 X
0
0 0
0
1 X
0
X X
0
z
X X
b y
x z
x z
x z
x z
X
x x x
Number Representation
Format: <size><base_format><number> <size> - decimal specification of bits count
Default: unsized and machine-dependent but at least 32 bits
Number Representation
Format: <size><base_format><number> <number> - value given in base of base format
_ can be used for reading clarity x and z are automatically extended
Number Representation
Examples:
6b010_111 8b0110 4bx01 16H3AB 24 5O36 16Hx 8hz gives gives gives gives gives gives gives gives 010111 00000110 xx01 0000001110101011 00011000 11110 xxxxxxxxxxxxxxxx zzzzzzzz
Number Representation
659 // unsized decimal h 837ff // unsized hexadecimal o7460 // unsized octal 4af // illegal syntax 4b1001 // 4-bit binary 5D 3 // 5-bit decimal 3b01x // 3-bit number with unknown LSB 12hx // 12-bit unknown 8d -6 // illegal syntax -8d 6 // phrase as - (8d6) // underline usage 27_195_000 16b0001_0101_0001_1111 32h12ab_f001 // X and Z is sign-extended reg [11:0] a; initial begin a = hx; xxx a = h3x; 03x a = h0x; 00x end
// yields // yields
// yields
Net Concatenation
Module B
Module A
3o7 Representations {b[3:0],c[2:0]} {a,b[3:0],w,3b101} {4{w}} {b,{3{a,b}}} Meanings
{b[3] ,b[2] ,b[1] ,b[0], c[2] ,c[1] ,c[0]} {a,b[3] ,b[2] ,b[1] ,b[0],w,1b1,1b0,1b1} {w,w,w,w} {b,a,b,a,b,a,b}
Module C
Operators
Arithmetic Operators Relational Operators Equality Operators Logical Operators Bit-wise Operators Unary Reduction Shift Operators Conditional Operators Concatenations +, -, *, /, % <, <=, >, >= ==, !=, ===, !== !, &&, || ~, &, |, ^, ~^ &, ~&, |, ~|, ^, ~^ >>, << ?: {}
Operator Examples
Compiler Directives
'define
'define RAM_SIZE 16 Defining a name and gives a constant value to it.
'include
'include adder.v Including the entire contents of other verilog source file.
'timescale
'timescale 100ns/1ns Setting the reference time unit and time precision of your simulation.
System Tasks
$monitor
$monitor ($time,"%d %d %d",address,sinout,cosout); Displays the values of the argument list whenever any of the arguments change except $time.
$display ("%d %d %d",address,sinout,cosout); Prints out the current values of the signals in the argument list $finish Terminate the simulation
$display
$finish
Outline
Introduction to Verilog HDL Syntax in Verilog HDL Gate-Level Modeling Test-Bench Compilation and Simulation Tools
Primitives
Primitives are modules ready to be instanced Smallest modeling block for simulator Verilog build-in primitive gate
and, or, xor, nand, nor, xnor
prim_name #delay inst_name( out0, in0, in1,.... );
not, buf
Ci 0 0
A 0 0 1 1 0 0 1 1
B 0 1 0 1 0 1 0 1
Co 0 0 0 1 0 1 1 1
S 0 1 1 0 1 0 0 1
Co
Full Adder S
Ci
0 0 1 1 1 1
37
Co
38
a b c
sum
39
a b b c c a
a b c
40
Outline
Introduction to Verilog HDL Syntax in Verilog HDL Gate-Level Modeling Test-Bench Compilation and Simulation Tools
Test Methodology
Systematically verify the functionality of a model. Procedure of simulation
Detect syntax violations in source code Simulate behavior Monitor results
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Test Methodology
Stimulus
Testbench
Response
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Verilog Simulator
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full_add M1 (sum, c_out, a, b, cin); //DUT initial #200 $finish; initial begin #10 a = 0; b = #10 a = 0; b = #10 a = 1; b = #10 a = 1; b = #10 a = 0; b = #10 a = 0; b = #10 a = 1; b = #10 a = 1; b = end endmodule 0; 1; 0; 1; 0; 1; 0; 1; cin cin cin cin cin cin cin cin = = = = = = = = // Stopwatch // Stimulus patterns 0; // Execute in sequence 0; 0; 0; 1; 1; 1; 1;
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Summary
Design module / DUT
Divide-and-Conquer Partition the whole design into several parts Architecture figure of each sub-module Make architecture figures before you write Verilog codes Create hardware design in gate-level or RT-level Connection of sub-modules
Test-bench
Feed input data and compare output values at right timing slots Usually describe in behavioral level Not real hardware, just like software programming (e.g. C/C++)
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Note
Verilog is a platform
Support hardware design (design module) Also support C/C++ like coding (test bench)
Hardware
Combinational circuits (todays topic) Sequential circuits (we wont model them in this course)
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Outline
Introduction to Verilog HDL Syntax in Verilog HDL Gate-Level Modeling Test-Bench Compilation and Simulation Tools
Workstations
Why workstations?
Multiple Users, multiple tasking Stable Operations
User Interface
Text Mode X-Window
Workstations
Where are the workstations?
http://cad.ee.ntu.edu.tw/ Please fill the application, and your account will be ready before 11/13.
NOTE: This account expires after this semester. If you want to continue enjoying the resources on the workstations, contact the TA managing the IC design Lab to get more information.
Usually you need to attend the Special Projects held by the professors in ICS or EDA group
Workstations
How can I connect to the workstations?
PCMan? KKMan? No! putty or pietty (Inherited from putty, dedicated to CJK environments) putty download site:
http://www.putty.org/
IP or Domain Name Session Name (the same as IP or Domain Name) Username and Password
Port: 22
Workstations
To make the programs available, we need to execute the following command:
source /usr/spring_soft/CIC/verdi.cshrc This command needs to be executed whenever you login.
Workstations
Basic instructions
Change Password: passwd Log out: logout Show processes: ps (processes and PIDs) Delete a process: kill -9 PID
Workstations
Useful commands
man : manual page ls : list a folders contents ls a : list all files (including the hidden files) ls aux : list all files with detailed information cp : copy files from one folder/directory to another cp filename1 filename2 cp r : copy the whole folder to another mkdir : create a folder pwd : display your current path
Workstations
More useful commands cd : Change folder ps : display process status by process identification number and name kill -9 PID: terminate a running process
rm : delete files rm r : remove the whole folder quota v : show disk space tar : pack and compress files
kill -9 1234
-cvf : for creating compressed file -xvf : for extracting compressed file
X-window
Why X-window?
Most important graphic user interface on UNIX and similar system
X-window
X-window
What X-window server can be used? X-Win32
http://www.starnet.com/products/xwin32/ Student Order : US$69.95
XFree86
http://www.xfree86.org/ Free Need Cygwin on MS Windows
Xming
http://www.straightrunning.com/XmingNotes/ Free for version 6.9.0.31, but donation necessary for version 7.5.0.11 Easy to setup We will use this as an example
X-window
Since X-window server runs on users clients, we usually need our clients to have public IP. What if we are using private IP, say, wireless network for example?
An example
PID
Useful Editors
vi
Powerful but not so user friendly Suitable for advanced users
gedit
graphic user interface Analogy with notepad in Windows Suitable for beginners We use this as the example
gedit
NC-verilog
Designed by Cadence Inherited from Verilog-XL
FA_sum.v
module FA_sum ( sum, a, b, ci ); input a, b, ci; output sum;
endmodule
endmodule