Basic Logic Design with Verilog HDL:

Gate-Level Design on Combinational Circuits

Lecture note

ver.1 ver.2 ver.3 ver.4 ver.5 ver.6

by by by by by by

Chen-han Tsai Chih-hao Chao Xin-Yu Shi Bo-Yuan Peng Cheng-Zhou Zhan Bo-Yuan Peng

Outline
Introduction to Verilog HDL Syntax in Verilog HDL Gate-Level Modeling Test-Bench Compilation and Simulation Tools

Outline
Introduction to Verilog HDL Syntax in Verilog HDL Gate-Level Modeling Test-Bench Compilation and Simulation Tools

What is Verilog HDL?

Why using Hardware Description Language?
Design abstraction: HDL layout by human Hardware modeling Reduce cost and time to design hardware

Two Popular HDLs

VHDL Verilog

What is Verilog HDL?

Key features of Verilog
Supports various levels of abstraction
Behavior level Register transfer level Gate level Switch level

Simulate design functions

Different Levels of Abstraction

Architectural / Algorithmic Level
Implement a design algorithm in high-level language constructs.

Register Transfer Level

Describes the flow of data between registers and how a design process these data.

Different Levels of Abstraction

Gate Level
Describe the logic gates and the interconnections between them.

Switch (Transistor) Level

Describe the transistors and the interconnections between them.

Simplified Hardware Design Flow

Designer

Level RTL Simulation RTL Editor

RTL Code

Cost Low

High

Verilog
Gate Level Simulation

Logic Synthesizer
Gate Level Code

Post Gate Level Simulation

Place & Route

Physical Layout

Tape Out

Low

High

Chip

Example: 1-bit Multiplexer

to select output

sel 0 out 1

sel 0 0 0 0 1 1 1 1

in1 0 0 1 1 0 0 1 1

in2 0 1 0 1 0 1 0 1

out 0 0 1 1 0 1 0 1

in1 in2

Gate Level Description

in1 in2
n1

iv_sel

a1 a2

a1_o

o 1

out

a2_o

sel

iv_sel

Gate Level: you see only netlist (gates and wires) in the code.

Outline
Introduction to Verilog HDL Syntax in Verilog HDL Gate-Level Modeling Test-Bench Compilation and Simulation Tools

A Simple Verilog Code

module name declaration syntax in/out port

port/wire declaration

kernel hardware gate-connection/ behavior

Module
Basic building block in Verilog Module
1. Created by declaration (cant be nested) 2. Used by instantiation

Interface is defined by ports May contain instances of other modules All modules run concurrently

Module Instantiation
Adder

instance example

Adder

Adder

Adder_tree

Instances
A module provides a template from which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters and I/O interface.

Analogy: Module vs. Class

Format

module m_Name( IO list ); ... endmodule m_Name ins_name ( port connection list ); ins_name.member_signal

class c_Name { ... }; c_Name obj_name; obj_name.member_data

Instantiation
Member

Hierachy

instance.sub_instance.me mber_signal

object.sub_object.member_ data

Port Connection

Connect module port by order list

FA1 fa1(c_o, sum, a, b, c_i);

Connect module port by name (Recommended)

Usage: .PortName (NetName)
FA1 fa2(.A(a), .B(b), .CO(c_o), .CI(c_i), .S(sum)); FA1 fa3(c_o, , a, b, c_i);

Not fully connected

Verilog Language Rule

Case sensitive Identifiers
Digits 0123456789 Underscore _ Upper and lower case letters from the alplabet

Terminate statement/declaration with semicolon ; Comments

Single line: // its a single line comment example Multi-line: /* When the comment exeeeds single line, multi-line comment is necesssary */

Data Type: Register

Register
Keyword: reg, integer, time, real Event-driven modeling Storage element (modeling sequential circuit) Assignment in always block (LHS of expressions)

Data Type: Net

Net
Keyword: wire, wand, wor, tri, triand, trior, supply0, supply1 Doesnt store value, just a connection Input, output and inout ports are default wire

Four-valued Logic Value

Nets and registers in Verilog codes hold four-valued data
0 represent a logic 0 or false condition 1 represent a logic 1 or true condition z
Output of an undriven tri-state driver High-Z value Models case where nothing is setting a wires value

Four-valued Logic Value

Nets and registers in Verilog codes hold four-valued data
x
Models when the simulator cant (doesnt) decide the value un-initialized or unknown logic value
Initial state of registers A wire is being driven to 0 and 1 simultaneously Output of a gate with z inputs

Logic System
Four values: 0, 1, x/X, z/Z (not case sensitive)
The logic value x denotes an unknown (ambiguous) value The logic value z denotes a highimpedance value (High-Z value)

Primitives have built-in Logic Simulators describe 4-value logic

Logic System: Example

a b a
0 1 x

0
1 X

0
0 0

0
1 X

0
X X

0
z

X X

b y

x z

x z

x z

x z

X
x x x

Number Representation
Format: <size><base_format><number> <size> - decimal specification of bits count
Default: unsized and machine-dependent but at least 32 bits

<base_format> - ' followed by arithmetic base of number

d h o b or or or or D decimal (default if no base format given) H hexadecimal O octal B binary

Number Representation
Format: <size><base_format><number> <number> - value given in base of base format
_ can be used for reading clarity x and z are automatically extended

Number Representation
Examples:
6b010_111 8b0110 4bx01 16H3AB 24 5O36 16Hx 8hz gives gives gives gives gives gives gives gives 010111 00000110 xx01 0000001110101011 00011000 11110 xxxxxxxxxxxxxxxx zzzzzzzz

Number Representation
659 // unsized decimal h 837ff // unsized hexadecimal o7460 // unsized octal 4af // illegal syntax 4b1001 // 4-bit binary 5D 3 // 5-bit decimal 3b01x // 3-bit number with unknown LSB 12hx // 12-bit unknown 8d -6 // illegal syntax -8d 6 // phrase as - (8d6) // underline usage 27_195_000 16b0001_0101_0001_1111 32h12ab_f001 // X and Z is sign-extended reg [11:0] a; initial begin a = hx; xxx a = h3x; 03x a = h0x; 00x end

// yields // yields

// yields

Net Concatenation
Module B
Module A
3o7 Representations {b[3:0],c[2:0]} {a,b[3:0],w,3b101} {4{w}} {b,{3{a,b}}} Meanings
{b[3] ,b[2] ,b[1] ,b[0], c[2] ,c[1] ,c[0]} {a,b[3] ,b[2] ,b[1] ,b[0],w,1b1,1b0,1b1} {w,w,w,w} {b,a,b,a,b,a,b}

Module C

Operators
Arithmetic Operators Relational Operators Equality Operators Logical Operators Bit-wise Operators Unary Reduction Shift Operators Conditional Operators Concatenations +, -, *, /, % <, <=, >, >= ==, !=, ===, !== !, &&, || ~, &, |, ^, ~^ &, ~&, |, ~|, ^, ~^ >>, << ?: {}

Excerpts from CIC training course: Verilog_9807.pdf

Operator Examples

All bits are 0 logic false

Excerpts from CIC training course: Verilog_9807.pdf

Compiler Directives
'define
'define RAM_SIZE 16 Defining a name and gives a constant value to it.

'include
'include adder.v Including the entire contents of other verilog source file.

'timescale
'timescale 100ns/1ns Setting the reference time unit and time precision of your simulation.

System Tasks
$monitor
$monitor ($time,"%d %d %d",address,sinout,cosout); Displays the values of the argument list whenever any of the arguments change except $time.
$display ("%d %d %d",address,sinout,cosout); Prints out the current values of the signals in the argument list $finish Terminate the simulation

$display

$finish

Outline
Introduction to Verilog HDL Syntax in Verilog HDL Gate-Level Modeling Test-Bench Compilation and Simulation Tools

Gate Level Modeling

Steps
Develop the Boolean function of output Draw the circuit with logic gates/primitives Connect gates/primitives with net (usually wire)

HDL: Hardware Description Language

Figure out architecture first, then write code.
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Primitives
Primitives are modules ready to be instanced Smallest modeling block for simulator Verilog build-in primitive gate
and, or, xor, nand, nor, xnor
prim_name #delay inst_name( out0, in0, in1,.... );

not, buf

User defined primitive (UDP)

prim_name #delay inst_name( out0, out1, ..., in0);

building block defined by designer

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Case Study: Full Adder

Ci 0 0

A 0 0 1 1 0 0 1 1

B 0 1 0 1 0 1 0 1

Co 0 0 0 1 0 1 1 1

S 0 1 1 0 1 0 0 1

Co

Full Adder S

Ci

0 0 1 1 1 1

37

Case Study: Full Adder

Co = AB + BCi + CiA
A B B Ci Ci A

Co

38

Case Study: Full Adder

sum = a b ci
a b c sum

a b c

sum

39

Case Study: Full Adder

Full Adder Connection
Instance ins_c from FA_co Instance ins_s from FA_sum
full adder carry out connection co

a b b c c a

a b c

sum connection sum

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Outline
Introduction to Verilog HDL Syntax in Verilog HDL Gate-Level Modeling Test-Bench Compilation and Simulation Tools

Test Methodology
Systematically verify the functionality of a model. Procedure of simulation
Detect syntax violations in source code Simulate behavior Monitor results

42

Test Methodology

Stimulus

Testbench

Hardware Design (Design Under Test)

Response

43

Verilog Simulator

44

Testbench for Full Adder

module t_full_add(); reg a, b, cin; wire sum, c_out; // for stimulus waveforms

full_add M1 (sum, c_out, a, b, cin); //DUT initial #200 $finish; initial begin #10 a = 0; b = #10 a = 0; b = #10 a = 1; b = #10 a = 1; b = #10 a = 0; b = #10 a = 0; b = #10 a = 1; b = #10 a = 1; b = end endmodule 0; 1; 0; 1; 0; 1; 0; 1; cin cin cin cin cin cin cin cin = = = = = = = = // Stopwatch // Stimulus patterns 0; // Execute in sequence 0; 0; 0; 1; 1; 1; 1;

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Summary
Design module / DUT
Divide-and-Conquer Partition the whole design into several parts Architecture figure of each sub-module Make architecture figures before you write Verilog codes Create hardware design in gate-level or RT-level Connection of sub-modules

Test-bench

Feed input data and compare output values at right timing slots Usually describe in behavioral level Not real hardware, just like software programming (e.g. C/C++)
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Note
Verilog is a platform
Support hardware design (design module) Also support C/C++ like coding (test bench)

How to write verilog well?

Know basic concepts and syntax Get a good reference codes (a person or some code files) Form a good coding style

Hardware
Combinational circuits (todays topic) Sequential circuits (we wont model them in this course)
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Outline
Introduction to Verilog HDL Syntax in Verilog HDL Gate-Level Modeling Test-Bench Compilation and Simulation Tools

Workstations
Why workstations?
Multiple Users, multiple tasking Stable Operations

How to run tasks on the workstations?

Operating System: Unix-like
Example: Linux Example: Solaris

User Interface
Text Mode X-Window

Workstations
Where are the workstations?
http://cad.ee.ntu.edu.tw/ Please fill the application, and your account will be ready before 11/13.
NOTE: This account expires after this semester. If you want to continue enjoying the resources on the workstations, contact the TA managing the IC design Lab to get more information.
Usually you need to attend the Special Projects held by the professors in ICS or EDA group

Workstations
How can I connect to the workstations?
PCMan? KKMan? No! putty or pietty (Inherited from putty, dedicated to CJK environments) putty download site:
http://www.putty.org/

pietty download site:

http://ntu.csie.org/~piaip/pietty/

In the following examples, we will use putty.

IP or Domain Name Session Name (the same as IP or Domain Name) Username and Password

Port: 22

Workstations
To make the programs available, we need to execute the following command:
source /usr/spring_soft/CIC/verdi.cshrc This command needs to be executed whenever you login.

Workstations
Basic instructions
Change Password: passwd Log out: logout Show processes: ps (processes and PIDs) Delete a process: kill -9 PID

Workstations
Useful commands
man : manual page ls : list a folders contents ls a : list all files (including the hidden files) ls aux : list all files with detailed information cp : copy files from one folder/directory to another cp filename1 filename2 cp r : copy the whole folder to another mkdir : create a folder pwd : display your current path

Workstations
More useful commands cd : Change folder ps : display process status by process identification number and name kill -9 PID: terminate a running process
rm : delete files rm r : remove the whole folder quota v : show disk space tar : pack and compress files
kill -9 1234

mv : move or rename file exit : turn the terminal off logout

-cvf : for creating compressed file -xvf : for extracting compressed file

X-window
Why X-window?
Most important graphic user interface on UNIX and similar system

How to use X-window?

You need an X-window server to use the X-window.
Not an X-window client. An X-window client is a program with GUI that runs on the workstations.

X-window

X-window
What X-window server can be used? X-Win32
http://www.starnet.com/products/xwin32/ Student Order : US$69.95

XFree86
http://www.xfree86.org/ Free Need Cygwin on MS Windows

Xming
http://www.straightrunning.com/XmingNotes/ Free for version 6.9.0.31, but donation necessary for version 7.5.0.11 Easy to setup We will use this as an example

Download and install these two

X-window
Since X-window server runs on users clients, we usually need our clients to have public IP. What if we are using private IP, say, wireless network for example?

1. Type the DN then save

2. Select X11 preference setup

3. Check Enable X11 forwarding

An example

Run firefox (& means simultaneously) NOTE: DONT DO IT OFTEN!

PID

Useful Editors
vi
Powerful but not so user friendly Suitable for advanced users

gedit
graphic user interface Analogy with notepad in Windows Suitable for beginners We use this as the example

gedit

Verilog-XL and NC-verilog

Verilog-XL
Designed by Phil Moorby, the father of verilog Interpreter of verilog Designed for syntax checking and simulation

NC-verilog
Designed by Cadence Inherited from Verilog-XL

In the following examples, we use NCverilog.

Example: Full Adder and its testbench

FA_co.v
module FA_co ( co, a, b, ci ); input a, b, ci; output co; wire ab, bc, ca; and and and or g0( g1( g2( g3( ab, bc, ca, co, a, b ); b, ci ); ci, a ); ab, bc, ca );

FA_sum.v
module FA_sum ( sum, a, b, ci ); input a, b, ci; output sum;

xor g0( sum, a, b, ci );

endmodule

endmodule

Example: Full Adder and its testbench

FA_gatelevel.v
module FA_gatelevel ( sum, co, a, b, ci ); input a, b, ci; output sum, co; FA_co ins_c( co, a, b, ci ); FA_sum ins_s( sum, a, b, ci ); endmodule

Example: Full Adder and its testbench

FA_tb.v
module FA_tb();
reg a, b, cin; wire sum, c_out; FA_gatelevel fa1 ( sum, c_out, a, b, cin ); initial #200 $finish; initial begin #10 #10 #10 #10 #10 #10 #10 #10 end a a a a a a a a = = = = = = = = 0; 0; 1; 1; 0; 0; 1; 1; b b b b b b b b = = = = = = = = 0; 1; 0; 1; 0; 1; 0; 1; cin cin cin cin cin cin cin cin = = = = = = = = 0; 0; 0; 0; 1; 1; 1; 1;

endmodule

Example: Full Adder and test-bench

Example: Full Adder and its testbench

How to observe the designed circuit?
debussy

Select the files then Add

Example: Full Adder and its testbench

How to observe the timing diagram?
$fsdbDumpfile("filename"); $fsdbDumpvars; nWave (part of debussy)

Double-click all of the signals you want to observe