COMPUTER ARCHITECTURE AND ASSEMBLY

LANGUAGE PROGRAMMING
Course Objectives
 To introduce principles of computer organization and the basic architectural
concepts

 Recommend instruction formats, addressing modes, micro instructions for

design of control unit

 Write assembly level programs using 8086 microprocessor

 Understand the I/O and memory organizations of a Computer system

 Recognize different parallel processing architectures

Course Outcomes

 Demonstrate an understanding of the design of the functional units of a

digital computer system

 Design micro instructions for different kinds of CPU organizations with proper
understanding of instruction formats and addressing modes

 Write assembly language programs using 8086 microprocessor with the

knowledge of pin diagram, registers and instruction formats of 8086
microprocessor

 Identify different hardware components associated with the memory and I/O
organization of a computer

 Differentiate different parallel processing architectures

 UNIT – I

Digital Computers: Introduction, Block diagram of Digital Computer,

Definition of Computer Organization, Computer Design and Computer
Architecture.

Register Transfer Language and Micro operations: Register Transfer

language, Register Transfer, Bus and memory transfers, Arithmetic
Micro operations, logic micro operations, shift micro operations,
Arithmetic logic shift unit.

Basic Computer Organization and Design: Instruction codes, Computer

Registers ,Computer instructions, Instruction cycle.
 CHAPTER 1: DIGITAL COMPUTERS

Introduction

Block diagram of Digital Computer

Definition of Computer Organization

Computer Design

Computer Architecture
Basic Terminology
Computer Software
A  A computer program that tells the
device that accepts input,
processes data, stores data, and computer how to perform a
produces output, all according to a particular task
series of stored instructions
Network
Hardware  Two or more computers and other
 Includes the electronic and devices that are connected, for the
mechanical devices that process purpose of sharing data and
the data; refers to the computer as programs
well as peripheral devices
Data Peripheral devices
 Used to expand the computer’s
Information input, output and storage
capabilities
Computing Systems
Computers have two kinds of components

Hardware, consists of physical devices (CPU, memory, bus, storage

devices, ...)

Software, consists of the programs such as (Operating system,

applications, utilities, ...)
FUNCTIONAL UNITS OF COMPUTER

Input Unit

Output Unit

Central processing Unit (ALU and Control Units)

Memory

Bus Structure
Input Unit:

Converts the external world data to a binary format, which can be

understood by CPU

Eg: Keyboard, Mouse, Joystick etc

Output Unit:

Converts the binary format data to a format that is human

understandable

Eg: Monitor, Printer, LCD, LED etc

CPU

• The “brain” of the machine

• Responsible for carrying out computational task

• Contains ALU, CU, Registers

• ALU Performs Arithmetic and logical operations

• CU Provides control signals in accordance with some timing

signals which in turn controls the execution process
Memory

Stores data, results, programs

Two classes of storage

(i) Primary (ii) Secondary

Two types are RAM or R/W memory and ROM read only memory

RAM is a form of computer data storage which

stores data and machine code currently being used

ROM is used to store data and program which is non volatile

Secondary storage is used for bulk storage or mass storage

Basic Operational Concepts

Basic Functions of Computer

 To Execute a given task as per the appropriate program

 Program consists of list of instructions stored in memory

At the most basic level, a computer is a device consisting of three

parts:

 A processor to interpret and execute programs

 A memory to store both data and programs
 A mechanism for transferring data to and from the outside world
Computer Organization And Architecture

Computer Organization is concerned with the way the hardware

components operate and the way they are connected together to form
the computer system

Computer design is concerned with the hardware design of the

computer

Computer architecture is concerned with the structure and behavior of

the computer as seen by the user
Chapter 2: Register Transfer and Micro operations

• Register Transfer Language

• Register Transfer

• Bus And Memory Transfers

• Arithmetic Micro operations

• Logic Micro operations

• Shift Micro operations

• Arithmetic Logic Shift Unit

 Registers

Registers are fast stand-alone storage locations that hold data temporarily.
Multiple registers are needed to facilitate the operations of the CPU.

Two registers - MAR (Memory Address Register) and MDR (Memory

Data Register) : To handle the data transfer between main memory and
processor.

MAR-Holds addresses
MDR-Holds data
Register Transfer Language (RTL)
Digital System: An interconnection of hardware modules that do a
certain task on the information

Registers + Operations performed on the data stored in them =

Digital Module

Modules are interconnected with common data and control paths to

form a digital computer system
Micro operations: operations executed on data stored in one or more
registers

For any function of the computer, a sequence of micro operations is

used to describe it

The result of the operation may be

 replace the previous binary information of a register or
 transfer to another register
The internal hardware organization of a digital computer is defined
by specifying:

 The set of registers it contains and their function

 The sequence of micro operations performed on the binary

information stored in the registers

 The control that initiates the sequence of micro operations

Registers + Micro operations Hardware + Control Functions =

Digital Computer
 Register Transfer

Computer registers are designated by capital letters to denote the

function of the register
 R1: processor register

 MAR: Memory Address Register (holds an address for a

memory unit)
 PC: Program Counter

 IR: Instruction Register

 SR: Status Register

R1 7 6 5 4 3 2 1 0

Register R1 Showing individual bits

Block diagram of a register

Information transfer from one register to another is described by a
replacement operator:

R2 ← R1

This statement denotes a transfer of the content of register R1 into

register R2
The transfer happens in one clock cycle
The content of the R1 (source) does not change
The content of the R2 (destination) will be lost and replaced by the
new data transferred from R1
Conditional transfer occurs only under a control condition

Representation of a (conditional) transfer

P: R2 ← R1
A binary condition (P equals to 0 or 1) determines when the transfer
occurs
The content of R1 is transferred into R2 only if P is 1
Bus and Memory Transfers

Paths must be provided to transfer information from one register to

another

A Common Bus System is a scheme for transferring information

between registers in a multiple-register configuration

A bus is a set of common lines, one for each bit of a register, through
which binary information is transferred one at a time

Control signals determine which register is selected by the bus

during each particular register transfer
 Register A Register B Register C Register D

Bus lines

Register D Register C Register B Register A

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

D3 D2 D1 D0 C3 C2 C1 C0 B3 B 2 B 1 B 0 A3 A 2 A 1 A 0

D3 C3 B3 A3 D2 C2 B2 A2 D1 C1 B1 A1 D0 C0 B0 A0

3 2 1 0 3 2 1 0 3 2 1 0
3 2 1 0 S0
S0 S0 S0
MUX3 MUX2 MUX1 MUX0 S1
S1 S1 S1

4-Line Common Bus

Bus System for four Registers
A bus system can be constructed with three-state buffer gates instead
of multiplexers

A three-state buffer is a digital circuit that exhibits three states: logic-

0, logic-1, and high-impedance (Hi-Z)

Control input C

Normal input A Output B

Three-State Buffer
Bus and Memory Transfers

S1 0
Select
S0 1
Bus line for bit 0
2×4 A0
Decoder 2
Enable E
3

B0

C0

D0

Three-State Bus Buffers

Memory Transfer
Memory read : Transfer from memory

Memory write : Transfer to memory

Assume that the address of a memory unit is stored in a register

called the Address Register AR

Lets represent a Data Register with DR, then:

Read: DR ← M[AR]
Write: M[AR] ← DR
Example

AR
x0C 19
x12 x0E 34
R1 x10 45
100 x12 66
x14 0
x16 13
R1←M[AR] x18 22

RAM

R1 R1
100 66
Arithmetic Micro operations

The micro operations most often encountered in digital computers

are classified into four categories:

 Register transfer micro operations

 Arithmetic micro operations (on numeric data stored in the
registers)
 Logic micro operations (bit manipulations on non-numeric data)
 Shift micro operations
The basic arithmetic micro operations are: addition, subtraction,
increment, decrement, and shift

Addition Micro operation:

R3 ←R1+R2
Subtraction Micro operation:
1’s complement
R3 ←R1-R2 or :
R3 ←R1+R2+1
One’s Complement Micro operation:
R2 ←R2

Two’s Complement Micro operation:

R2 ←R2+1

Increment Micro operation:

R2 ←R2+1

Decrement Micro operation:

R2 ←R2-1
Binary Adder

B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1
FA FA FA FA C0

C4 S3 S2 S1 S0

4-Bit Binary Adder (connection of FAs)

Binary Adder- Subtractor
B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1 C0
FA FA FA FA

C4 S3 S2 S1 S0

4-Bit Adder- Subtractor

A3 A2 A1 A0 1

x y x y x y x y

HA HA HA HA

C S C S C S C S

C4 S3 S2 S1 S0

4-Bit Binary Incrementer

Arithmetic Micro operations

Arithmetic Circuit

This circuit performs seven distinct arithmetic operations and the

basic component of it is the parallel adder

The output of the binary adder is calculated from the following

arithmetic sum: D = A + Y + Cin
 A3 A2 A1 A0
1 0 B3 B3 S1 S0 1 0 B2 B2 S1 S0 1 0 B1 B1 S1 S0 1 0 B0 B0 S1 S0

3 2 1 0 S 1 S0 3 2 1 0 S 1 S0 3 2 1 0 S 1 S0 3 2 1 0 S 1 S0

4×1 MUX 4×1 MUX 4×1 MUX 4×1 MUX

Y3 X3 Y2 X2 Y1 X1 Y0 X0
C3 C2 C1
FA FA FA FA Cin

Cout D3 D2 D1 D0

4-Bit Arithmetic Circuit

Logic Micro operations: The four basic micro operations

OR Micro operation
Symbol: , +

Gate:

Example: if the 2 input bits are 0, then the output is 0

 AND Micro operation

Symbol: 

Gate:

Example: if the 2 input bits are 1, then the output is 1

 Complement (NOT) Micro operation

Symbol: −

Gate:

Example: 1010 = 0101

 XOR (Exclusive-OR) Micro operation

Symbol: 

Gate:

Example: 1001  1010 = 0011

 NAND Micro operation

Symbols:  and 

Gate:

Example: if the 2 input bits are 1, then the output is 0

 NOR Micro operation

Symbols:  and 

Gate:

Example: if the 2 input bits are 0, then the output is 1

Hardware Implementation

The hardware implementation of logic micro operations requires that

logic gates be inserted for each bit or pair of bits in the registers to
perform the required logic function

Most computers use only four (AND, OR, XOR, and NOT) from
which all others can be derived.
 Logic Diagram Functional Table

S1
4×1
S0 S1 S0 Output Operation
MUX
Ai 0 0 E=AB XOR
Bi
0 0 1 E=AB OR

1 0 E=AB AND
1 Ei 1 1 E=A Complem
ent

One Stage of Logic Circuit

Shift Micro operations

Used for serial transfer of data

Also used in conjunction with arithmetic, logic, and other data-

processing operations

The contents of the register can be shifted to the left or to the right

As being shifted, the first flip-flop receives its binary information
from the serial input

Three types of shift: Logical, Circular, and Arithmetic

 Serial Input r2 Serial Output
rn-1 r3 r1 r0

Determines Shift Right

the “shift”
type

Serial Output Serial Input

rn-1 r3 r2 r1 r0

Shift Left
Transfers 0 through the serial input

Logical Shift Right: R1←shr R1

Logical Shift Left: R2←shl R2

? rn-1 r3 r2 r1 r0 0

Logical Shift Left

Logical Shift by one bit
Circulates the bits of the register around the two ends without loss of
information

Circular Shift Right: R1←cir R1

Circular Shift Left: R2←cil R2

rn-1 r3 r2 r1 r0

Circular Shift Left

Shifts a signed binary number to the left or right

An arithmetic shift-left multiplies a signed binary number by 2:

ashl (00100): 01000

An arithmetic shift-right divides the number by 2 ashr (00100) :

00010

An overflow may occur in arithmetic shift-left, and occurs when the
sign bit is changed (sign reversal)
 rn-1 r3 r2 r1 r0
?

Sign Arithmetic Shift Right

Bit

? rn-1 r3 r2 r1 r0 0
Sign
Arithmetic Shift Left
Bit
 Serial Input IR Serial Input IL
A3A2 A1 A0

Select

S 1 0 S 1 0 S 1 0 S 1 0 0 for shift right

1 for shift left
MUX MUX MUX MUX

H3 H2 H1 H0

4-Bit Combinational Circuit Shifter

Arithmetic Logic Unit

Instead of having individual registers performing the micro

operations directly, computer systems employ a number of storage
registers connected to a common operational unit called an
Arithmetic Logic Unit (ALU)
 S3
S2
S1 Ci
S0

One stage of Di
arithmetic
circuit (Fig.A)
Select
Fi
Ci+1 0 4×1
1 MUX
One stage of Ei 2
logic circuit
Bi (Fig.B) 3
Ai
shr
Ai+1
shl
Ai-1

One Stage of ALU

Chapter 3: Basic Computer Organization And Design

• Instruction codes

• Computer Registers

• Computer Instructions

• Instruction cycle
Instruction Codes

The Internal organization of a digital system is defined by the

sequence of micro operations it performs on data stored in its
registers

The user of a computer can control the process by means of a

program

A program is a set of instructions that specify the operations,

operands, and the processing sequence
A computer instruction is a binary code that specifies a sequence of
micro-operations for the computer. Each computer has its unique
instruction set

Instruction codes and data are stored in memory

The computer reads each instruction from memory and places it in a

control register

The control unit interprets the binary code of the instruction and
proceeds to execute it by issuing a sequence of micro-operations

An instruction code is usually divided into operation code, operand

address, addressing mode, etc.,
Stored Program Organization
Instruction Format
15 12 1 0 Memory
Opcode
1
Address 15
4096x16 0

Instructions
15 0
(program)
Binary Operand

Operands
(data)

15 0

Processor register
(Accumulator AC)
 Indirect Address

There are three Addressing Modes used for address portion of the
instruction code:

 Immediate: the operand is given in the address portion (constant)

 Direct: the address points to the operand stored in the memory
 Indirect: the address points to the pointer (another address) stored
in the memory that references the operand in memory

One bit of the instruction code can be used to distinguish between

direct & indirect addresses
 Instruction Format Effective
15 14 12 11 0 address
I Opcode Address

Direct Address Indirect address

22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand

1350 Operand

+ +
AC AC
Computer Registers
Computer instructions are normally stored in consecutive memory
locations and executed sequentially one at a time

The control reads an instruction from a specific address in memory

and executes it, and so on

This type of sequencing needs a counter to calculate the address of

the next instruction after execution of the current instruction is
completed

It is also necessary to provide a register in the control unit for storing
the instruction code after it is read from memory
 Registers in the Basic Computer
11 0
PC
11 0
AR Memory

15 0 4096 x 16
IR
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
Computer Registers - Common Bus System

S2S1S0: Selects the register/memory that would use the bus

LD (load): When enabled, the particular register receives the data
from the bus during the next clock pulse transition

E (extended AC bit): flip-flop holds the carry

DR, AC, IR, and TR: have 16 bits each

AR and PC: have 12 bits each since they hold a memory address
 S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1

LD INR CLR
PC 2

LD INR CLR

DR 3

LD INR CLR

Adder E
and AC 4
logic
LD INR CLR

INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus

Computer Registers Connected to a Bus

Computer Instructions
Basic Computer Instruction code format

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0
1 1 1 1 I/O operation
BASIC COMPUTER INSTRUCTIONS
Hex Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
Instruction Cycle
A program is a sequence of instructions stored in memory
The program is executed in the computer by going through a cycle for
each instruction (in most cases)
Each instruction in turn is subdivided into a sequence of sub-cycles or
phases
Instruction Cycle Phases:
- Fetch an instruction from memory
- Decode the instruction
- Read the effective address from memory if the instruction has an
indirect address
- Execute the instruction
This cycle repeats indefinitely unless a HALT instruction is
encountered
 Fetch and Decode
Initially, the Program Counter (PC) is loaded with the address of the
first instruction in the program

The sequence counter SC is cleared to 0, providing a decoded timing

signal T0

After each clock pulse, SC is incremented by one, so that the timing

signals go through a sequence T0, T1, T2, and so on

 T0: AR←PC (this is essential!!)

The address of the instruction is moved to AR.
T1: IR←M[AR], PC←PC+1
The instruction is fetched from the memory to IR ,
and the PC is incremented
T2: D0,…, D7←Decode IR(12-14), AR←IR(0-11), I←IR(15)
 Start
SC 

T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D'7IT3: AR ←M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.