COMPUTER ORGANIZATION

AND ARCHITECTURE

Unit-3: Control Design & Processor Organization

Execution of a Complete Instruction
• A program residing in the memory unit of the computer consists of a sequence
of instructions
• The program is executed by going through a cycle for each instruction
• Each instruction cycle is divided into a sequence of phases:

 Fetch an instruction from the memory

 Decode the instruction
 Read the effective address from the memory if the instruction has indirect
address
 Execute the instruction

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 • No. of bits required by an opcode depends on the total no. of operations available
in a computer.

• Rule of thumb; An opcode must have atleast n no. of bits for a given 2n operations

• The operation specified in the opcode has to be performed on some data,

therefore the instruction code must also specify the processor registers or the
memory location where operands are stored and also the location where result
must be stored

• Memory locations are specified by their address while processor registers may
be specified by a k bit binary number for 2k registers

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Instruction code
• A computer instruction is basically a binary code that specifies a sequence of
micro-operations to be performed by computer
• The computer then reads each instruction from memory and places it in a
control register
• The control unit then interprets the binary code and executes it

 Instruction code is a group of bits used to instruct the computer to perform a

specific operation

Operation code is a group of bits that define the operation to be performed like
add, subtract shift etc.
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Stored program organization
• Instructions are stored in one part of
the memory and data is placed in
another part

• 4096 memory locations of 16 bit each

• 12 bits are required for specifying the

address and remaining 4 bits can be
used for the opcode for 16 possible
operations

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 • Control reads the 16-bit instruction from the program portion of the memory

• Uses the 12 bit address part to read the operand from data portion of the
memory

• Executes the operation specified by the opcode

• Accumulator (AC) is used to store the result of the instruction execution

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 • The instruction consists of a 12-
bit address, 3-bit opcode and 1
bit I for indirect address mode.

• I = 0 for direct address and 1 for

indirect address

• Effective address is the address

of the operand

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• Computer Registers

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• Instruction format
The basic computer follows 3 instruction formats each having 16-bit representation

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• Memory reference instruction
12 bits are used to specify an address, 3 bits are for opcode, 1 bit specifies the
addressing mode

• Register reference instruction

Identified by the opcode 111 with 0 in the MSB. Theses instructions are operated on
the Accumulator register hence the memory operand is not required and thus the
remaining 12 bits are used to specify the operation to be performed

• Input-output instruction
Identified by the opcode 111 with 1 in the MSB. The memory operand is not required
and thus the remaining 12 bits are used to specify the I/O operation to be performed

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 • If the 2nd part of the instruction code specifies an operand instead of an address
then the instruction is said to have an immediate operand

• If the 2nd part of the instruction code specifies the address of the operand then
the instruction is said to have direct address

• If the 2nd part of the instruction code specifies the address of the memory
location where the address of operand is stored then the instruction is said to
have indirect address

• To differentiate between direct and indirect address, one bit of instruction code
is used.
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Timing and Control
• The timing of all registers is controlled by the master clock generator. The control
signals regenerate the control unit provide inputs to multiplexers, flags, common
bus and processor registers
• 2 main types of control organization: hard-wired control and micro-programmed
control

• In hard-wired control, the control logic is implemented with gates, flip-flops,

decoders and other digital circuits.
• In micro-programmed organization, the control information is stored in a control
memory which is programmed to initiate the required sequence of micro-
operations

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• Control unit

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• The 4-bit sequence counter can count form binary 0 to binary 15 which are
decoded and result in the generation of 16 timing signals T0 to T15.

• e.g. Consider a case where SC is incremented to provide timing signals T0-T4. At

the time T4, SC is cleared to 0 when decoder output D3 is active.

• SC responds to the 1st positive transition of the clock. Initially the CLR input of SC
is active.
• During 1st positive transition, SC is cleared to 0which activates the timing signal
T0.
• At every positive transition of clock the SC is incremented thus producing timing
signals T0, T1, T2, T3, T4.
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• Instruction cycle
• Fetch and Decode
Initially, the program counter PC is loaded with the address of the first instruction
in the program.
The sequence counter SC is cleared to 0, providing a decoded timing signal T0.
After each clock pulse, SC is incremented by one, so that the timing signals go
through a sequence T0, T1, T2, and so on.

The RTL statements for this phase are:

T0: AR ← PC
T1: IR ← M[AR], PC ← PC+1
T2: D0---D7 ← Decode IR (12-14), AR ← IR (0-11), I ← IR (15)
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• At T0, the address form PC is shifted to AR.
• The instruction is then read from the memory and placed in the IR when clock
signal transitions to T1. At the same time PC is incremented by 1 to hold the
address of next instruction to be used.
• At time T2, opcode in the IR is decoded and indirect bit is transferred to flip-flop
I.
• The address part of instruction is transferred to AR

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• Determining type of instruction
After decoding, timing signal becomes T3. During this time the control unit
determines the type of instruction read from the memory.
D7 is equal to 1 if opcode is 111, the instruction is a register reference or I/O
reference instruction.
If D7 = 0, opcode can be anything between 000 to 110 indicating that instruction is
a memory-reference instruction

After this the 1st bit of instruction stored in flip-flop I is checked. If D7 = 0, I = 1,

then we have memory-address instruction with indirect address. So the next step
is to read the effective address from memory
AR ← M[AR]
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• Types of instructions
Following set of instructions must be included by a computer

 Arithmetic, logical and shift instructions

 Instructions for moving information to and from memory and processor registers
 Program control instructions together with instructions that check status
conditions
 Input and output instructions

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Bus architecture
• Single bus architecture: In a single bus structure, one common bus is used to
communicate between peripherals and microprocessors. It has disadvantages
due to the use of one common bus.

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Bus architecture
• Parts of a System bus: Processor, memory, Input and output devices are connected by system bus,
which consists of separate buses

(i)Address bus: Address bus is used to carry the address. It is unidirectional bus. The address is sent to
from CPU to memory and I/O port and hence unidirectional. It consists of 16, 20, 24 or more parallel
signal lines.

(ii)Data bus: Data bus is used to carry or transfer data to and from memory and I/O ports. They are
bidirectional. The processor can read on data lines from memory and I/O port and as well as it can write
data to memory. It consists of 8, 16, 32 or more parallel signal lines.

(iii)Control bus: Control bus is used to carry control signals in order to regulate the control activities. They
are bidirectional. The CPU sends control signals on the control bus to enable the outputs of addressed
memory devices or port devices. Some of the control signals are: MEMR (memory read), MEMW (memory
write), IOR (I/O read), IOW (I/O write), BR (bus request), BG (bus grant), INTR (interrupt request), INTA
(interrupt acknowledge), RST (reset), RDY (ready), HLD (hold), HLDA (hold acknowledge)
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Single Accumulator based CPU Organization
• The computers, present in the early days of computer history, had accumulator
based CPUs. In this type of CPU organization, the accumulator register is used
implicitly for processing all instructions of a program and store the results into
the accumulator.
• The instruction format that is used by this CPU Organization is one address field.
Due to this the CPU is known as One Address Machine.

• In this CPU Organization, the first ALU operand is always stored into the AC
register and the second operand is present either in Registers or in the Memory.
• AC register is the default address thus after data manipulation the results are
stored into the AC register

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• Multiple bus architecture: In a multiple bus structure, one bus is used to fetch
instructions while other is used to fetch data, required for execution. It is to
overcome the bottleneck of a single bus structure.

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• The format of instruction is: Opcode + Address
• It uses LOAD and STORE instructions for data transfer: e.g. LOAD X, STORE Y

• Here LOAD is memory read operation that is data is transferred from memory
location X to accumulator and STORE is a memory write operation that is data is
transferred from accumulator to memory location Y.

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General Register Organization
• Memory locations in a computer can be used to store the pointers, counters,
return addresses, temporary results etc. during instruction execution.
• This memory access is very time-consuming so registers included in the CPU
were used to store the intermediate values and each register was connected to
other through a common bus

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 • The output of each register is connected to two multiplexers (MUX) that form
two buses A and B.
• Using the select lines of MUX, one register or input data for that bus is selected
• The buses A and B give the output to the ALU.
• OPR input of ALU selects the micro-operation to be performed on the data.
• The result of micro-operation is available as output and also goes to inputs of all
the registers.
• The decoder selects the register that stores the result of output by activating the
Load (LD) signal of that register.

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 • As an example

• MUX A selector (SELA) is used to place contents of register R2 into bus A

• MUX B selector (SELB) is used to place contents of register R3 into bus A
• ALU operation (OPR) provides the arithmetic addition micro-operation
• Decoder selector (SELD) is used to transfer the contents of output bus into R1

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 Control Word
• Specified by a combination of 14 binary selection inputs

• 3 bits of SELA select source register for input A

• 3 bits of SELB select source register for input B
• 3 bits of SELD select the destination register to store the output
• 5 bits of OPR select one of the micro-operations

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 Field SELA SELB SELD OPR
Symbol R2 R3 R1 SUB
Control Word 010 011 001 00101

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Stack Organization
• Stack is a storage device that stores information in a manner that item stored
last is the first to be retrieved.
• In digital computers, stack is a memory unit with an address register called stack
pointer (SP). SP holds the address of the top of the stack.

• Two operations of stack are insertion (Push) and deletion (Pop) of items which
are simulated by incrementing or decrementing the stack pointer register

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 • Stack can be placed in a portion of large memory
or it can be organized as a collection of finite
memory words or registers

Register stack
• SP contains binary numbers whose value is the
address of the memory word that is currently on
the top of stack
• The one-bit register FULL is set to 1 when stack is
full and register EMTY is set to 1 when stack is
empty

• DR holds the binary data to be written into or

read out of the stack
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• Initial values: SP = 0, EMTY = 1, FULL = 0

PUSH operation
Increment SP
Write item on top of stack
Check if stack is full
Mark the stack non-empty

POP operation
Read item from the top of stack
Decrement the SP
Check if stack is empty
Mark the stack not full
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Memory Stack
A stack can be implemented in the CPU by
assigning a portion of memory to a stack and a
processor register is used as a stack pointer.

• Initial value of SP will be 4001 and as addresses

decrease, the stack grows. The 1st item to be
stored in stack is placed at address 4000 and
last address that stack can use is 3000.

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• For push operation

• For pop operation

• In case of memory stack no separate provision is there for checking overflow or

underflow of the stack. The limits can be checked by using processor registers to
hold the values of upper limit and lower limit.
• After push operation, SP is compared with upper-limit register and after pop
operation, SP is compared with lower-limit register
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• Reverse polish notation
Stack organization is useful for evaluating arithmetic expressions.
Generally, the arithmetic operations are written in infix notation, i.e. each operator is written
between the operands
A*B+C*D
For stack manipulation, the reverse Polish notation is used where the operator is placed after the
operands.
Expression A * B + C * D can be written as AB * CD*+ in reverse Polish notation
 Scan the expression from left to right.
 When an operator is reached, perform the operation with the two operands found on left side
of the operator.
 Remove the two operands and operator and replace them with the result of the operation.
 Continue to scan the expression and repeat for every operator till no more operators are left.
• The conversion of infix notation to RPN must take into consideration the operation hierarchy.
1st perform the arithmetic operations inside inner parentheses and then inside outer
parantheses.

e.g. (3 * 4) + (5 * 6)
In RPN: 34 * 56 * +
Instruction Formats
• The instruction format symbolizes the bits of instruction as they appear in
memory words of control register
• Fields of instruction format
Operation code (Opcode) field: Specifies the operation to be performed
Address field: Designates a memory address or a processor register
Mode field: Specifies the way an operand or effective address is determined

• Opcode field contains a group of bits that define various processor operations like
add, subtract, complement
• Operands residing in memory are specified by memory address and operands
residing in the processor registers are specified by a register address
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• Mode field specifies a variety of ways for choosing operands from the given
address

• The instructions may have different lengths as per the number of addresses.
• The number of address fields depends on the internal organization of CPU and its
registers

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• Three address instruction

ADD R1, A, B ---------------------------

ADD R2 C, D ----------------------------
MUL X, R1, R2 --------------------------

Two address instruction

MOV R1, A -------------------
ADD R1, B -------------------
MOV R2, C -------------------
ADD R2, D -------------------
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MUL R1, R2 ----------------
MOV X, R1 -----------------

One address instruction

LOAD A ----------
ADD B ------------
STORE T ----------
LOAD C ----------
ADD D ------------
MUL T ----------
STORE X--------
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Zero address instruction
PUSH A ------------
PUSH B ------------
ADD -----------------
PUSH C --------------
PUSH D --------------
ADD ------------------
MUL ------------------
POP X -----------------

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Addressing Modes
• The way operands are chosen during a program execution depends on the
addressing mode of the instruction.
• The addressing mode specifies the rule for interpreting or modifying the address
field of the instruction before operand is referenced

• Most addressing modes modify the address field of the instruction but 2 modes
don’t use address field (Implied mode and Immediate mode)

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• Implied Mode: Operands are specified implicitly in the definition of the
instruction e.g. Complement Accumulator.

• Immediate mode: Operand is specified in the instruction itself. i.e. Instruction has
an operand field rather than intermediate field

• Register mode: Operands are stored in registers within the CPU.

• Register indirect mode: Instruction specifies a register that holds the address of
the memory location where operand is located

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• Indexed addressing mode: The contents of the index register are added address
part of the instruction to obtain the effective address

• Base register addressing mode: The contents of the base register are added to
the address part of the instruction to obtain the effective address.

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• Autoincrement/Autodecrement mode: The register is incremented or
decremented after its value has been used to access the memory

• Direct address mode: The effective address of the operand is equal to the address
part of the instruction

• Indirect address mode: The address field of the instruction gives the address of
memory location where the operand is actually located

• Relative address mode: the contents of the PC are added to the address part of
the instruction in order to obtain the effective address

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• Instruction is stored in two addresses: 200 and 201
PC= 200 to fetch the instruction
Mode field specifies the addressing mode

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Data transfer and Manipulation
• Computer instructions can be divided into 03 categories
 Data transfer: Transfer of data from one location to other
 Data manipulation: Performing some arithmetic or logic or shift operations on
data
 Program control: Provide decision-making capabilities and change the path of
the program when executed

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Data transfer instructions

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Data manipulation instructions

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Program control instructions

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Status bit conditions

Status bits or flag bits are supplemented with ALU.

04 main status bits: C (Carry), S (Sign), Z (Zero), V (Overflow)

Carry bit is set to 1 if the end carry is 1.

Sign bit is set to 1 if MSB is 1
Zero bit is set to 1 if the ALU operation results in all 0’s
Overflow bit is set to 1 if the Ex-OR of last two carries is 1 (When negative numbers
are in signed 2’s complement format)

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