COMPUTER ORGANIZATION

AND ARCHITECTURE

Unit-2: Computer Arithmetic

Unsigned numbers
• Unsigned binary numbers are represented as magnitude only no bit is reserved
for sign.

e.g. representing decimal numbers into unsigned binary numbers using 3-bits
Decimal No. Binary equivalent (3-bit binary unsigned numbers)
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
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Introduction
• Arithmetic operations are used in digital computers to manipulate the binary
data to produce results that can be used for solution of a particular
computational problem.

• The binary data on which the arithmetic operations are performed can be
represented in signed or unsigned format.

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Signed numbers
• Signed binary numbers are represented by magnitude and sign. The MSB is
reserved as sign bit while remaining n-1 bits represent the magnitude
e.g. representing decimal numbers into signed binary numbers using 3-bits

Decimal No. Binary equivalent (3-bit binary signed numbers)

0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
‒0 1 0 0
‒1 1 0 1
‒2 1 1 0
‒3 1 1 1
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• When an integer binary number is positive, it’s sign is represented as 0 and
magnitude is represented as binary equivalent number.

• When the number is negative, the sign is represented as 1 and magnitude is

represented in one of the three ways:
 Signed magnitude representation
 Signed 1’s complement
 Signed 2’s complement

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• Signed magnitude representation
e.g. ‒ 7 to be represented using 8-bits
MSB is sign bit: 1 in this case
Remaining bits represent the number 7 into equivalent binary value
1 0000111

• Signed 1’s complement representation

MSB is sign bit: 1 in this case
Remaining bits represent the number into 1’s complement of equivalent binary
value
e.g. ‒ 7 to be represented using 8-bits
1 1111000
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• Signed 2’s complement representation
MSB is sign bit: 1 in this case
Remaining bits represent the number into 2’s complement of equivalent binary
value
e.g. ‒ 7 to be represented using 8-bits
1 1111001

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Case 3: Both numbers have different signs

This is the 2’s complement

representation of binary
number (+7)

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• Arithmetic Addition
Case 1: Both numbers are positive

Case 2: Both numbers are negative

This is the 2’s complement

representation of binary
number (+19)

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Algorithms for Arithmetic Operations

• Addition and subtraction with signed-magnitude data

• Addition {subtraction) algorithm: when the signs of A and B are identical
(different), add the two magnitudes and attach the sign of A to the result.
• When the signs of A and B are different (identical), compare the
magnitudes and subtract the smaller number from the larger. Choose the
sign of the result to be the same as A if A > B or the complement of the sign
of A if A < B. If the two magnitudes are equal, subtract B from A and make
the sign of the result positive.
• The two algorithms are similar except for the sign comparison. The
procedure to be followed for identical signs in the addition algorithm is the
same as for different signs in the subtraction algorithm, and vice versa.
• Hardware implementation

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Algorithms for Arithmetic Operations
• Addition and subtraction with signed-magnitude data

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 • Addition and subtraction with signed-2’s complement data
Addition of two numbers consists of adding the numbers with sign bits treated as
other bits. Carry out of MSB is neglected.
Subtraction consists of 1st taking 2’s complement of subtrahend and then adding it
to the minuend.

• Hardware implementation

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• Hardware algorithm
For the flowchart of
addition/subtraction of
numbers in signed-magnitude
representation, indicate the
overall path the algorithm
takes for the following
(Assume MSB to be sign bit).
Also indicate status of AVF
(i) 0101101 + 0011111
(ii) 0101101 – 0101101
(iii) 1011111 - 0101101

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 • Multiplication of signed-magnitude data

• For implementation in digital computers,

Adder is used to add 2 binary numbers and accumulator stores the partial
products successively
Instead of shifting multiplier to left, the partial product is shifted to right

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• Hardware algorithm

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• Hardware implementation

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Hardware implementation
• First, instead of providing registers to store and add simultaneously as
many binary numbers as there are bits in the multiplier, it is convenient
to provide an adder for the summation of only two binary numbers and
successively accumulate the partial products in a register.
• Second, instead of shifting the multiplicand to the left, the partial
product is shifted to the right, which results in leaving the partial
product and the multiplicand in the required relative positions.
• Third, when the corresponding bit of the multiplier is 0, there is no
need to add all zeros to the partial product since it will not alter its
value.
• The multiplicand is stored in register B and multiplier is stored in register Q.
• Initially register A and E are set to 0.
• The sum of A and B forms the partial product stored in EA
• The final multiplication result is stored in AQ. A: Most significant bit, Q: Least
significant bit
• Sequence counter holds the value equal to no. of bits in multiplier (Q)
• Initially, the multiplicand is in register B and the multiplier in Q. The sum of A and B
forms a partial product which is transferred to the EA register. Both partial product
and multiplier are shifted to the right. This shift will be denoted by the statement
shr EAQ to designate the right shift. The least significant bit of A is shifted into the
most significant position of Q, the bit from E is shifted into the most significant
position of A, and 0 is shifted into E. After the shift, one bit of the partial product is
shifted into Q, pushing the multiplier bits one position to the right.
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• Numerical example

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• Hardware algorithm

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 Booth’s multiplication algorithm
Used for multiplying integers represented in signed-2’s complement format

Hardware implementation

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• Hardware algorithm

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Rules to follow for Booth’s Algorithm
1. The multiplicand is subtracted from the partial product upon
encountering the first least significant 1 in a string of 1's in the
multiplier.
2. The multiplicand is added to the partial product upon encountering
the first 0 (provided that there was a previous 1) in a string of 0’s in the
multiplier.
3. The partial product does not change when the multiplier bit is
identical to the previous multiplier bit.
Booth’s multiplication algorithm
• Booth algorithm gives a procedure for multiplying binary integers in
signed-2's complement representation. It operates on the fact that
strings of 0's in the multiplier require no addition but just shifting, and
a string of l's in the multiplier from bit weight 2k to weight 2m can be
treated as 2k+1 - 2m. For example, the binary number 001110 (+14) has
a string of l's from 23 to 21
• (k =3, m =1). The number can be represented as 2k+1 - 2m = 24 -21 = 16 -
2 = 14. Therefore, the multiplication M x 14, where M is the
multiplicand and 14 the multiplier, can be done as M x 24 - M x 21.
Thus the product can be obtained by shifting the binary multiplicand
M four times to the left and subtracting M shifted left once.
• Numerical example of (-9) X (-13) = (+117)

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 • Division of signed-magnitude data

• For implementation in digital computers,

Instead of divisor to right, the partial remainder is shifted to left.
Subtraction is achieved by adding A to the 2’s complement of B
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• The divisor is stored in register B and double-length dividend is stored in registers
A and Q.
• The dividend is shifted to the left and divisor is subtracted by adding it’s 2’s
complement value.
• The information about relative magnitude is stored in E
• If E=1 then A 1 is inserted in bit Qn and partial remainder is shifted to left to
repeat the process.
• If E=0, then . Qn remains 0 and value of B is added to restore the partial
remainder A.
• The partial remainder is shifted to left and process is repeated until all five
quotient bits are formed.
• At the end quotient is in Q and final remainder is in A.
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• Hardware algorithm for Signed-Magnitude Data

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• Numerical example

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• Divide overflow

Before showing the algorithm in flowchart form, we have to consider the

sign of the result and a possible overflow condition. The sign of the quotient
is determined from the signs of the dividend and the divisor. If the two signsare
alike, the sign of the quotient is plus. If they are unalike, the sign is minus.
The sign of the remainder is the same as the sign of the dividend.

When dividend is twice as long as the divisor, divide overflow occurs if high-order
half bits of dividend constitute a number greater than or equal to the divisor.

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Floating point representation
• Under this representation, the numbers are represented using 2 parts
 Mantissa (fixed point number)
 Exponent (position of decimal point)

e.g. + 6132.789
Fraction part: 0.6132789, exponent part: +4

Format for representation used:

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• Number needs to be stored in registers

Format followed
Sign (S) Exponent (E) Mantissa (M)

Biased unsigned value Signed normalized fraction

n: no. of bits used to store the exponent

Bias

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Normalization Implicit normalization: before decimal point
there should be a digit 1
1.0111 x 22
M= 0111, e = 2
101.11
Explicit normalization: before decimal point
there should be no digit
0.10111 x 23
M=10111, e = 3
Explicit normalization is the default normalization in conventional
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 Getting the number from floating point representation

Explicit normalization

Implicit normalization

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 Numerical example
Represent (+19.25)10 in floating point format using a 16-bit register for storing the
number. Mantissa follows explicit normalization and exponent is represented in
excess-32 format.
bias = 32, no. of bits used to store exponent = 6
No. of bits used to store sign bit =1
No. of bits used to store the mantissa = 16-(6+1) = 9

(+19.25)10  (10011.01)2 S E M
Normalization: 10011.01 0 100101 100110100
1 bit 6 bits 9 bits

M = 1001101, E = 5 + 32 = 37  100101
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IEEE format for floating point representation
• Disadvantage of conventional approach:
 Cannot represent number 0
 Cannot represent very small numbers

If E = all 0s or E = all 1s, then the numbers are special numbers

Sign (S) Exponent (E) Mantissa (M) Equivalent Number
0 000…0 000…0 +0
1 000…0 000…0 - 0
0 111…1 000…0 +∞
1 111…1 000…0 -∞
0/1 111…1 ≠0 Not a number (NaN)
0/1 000…0 ≠0 De-normalized number

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 Numerical example
Represent (-27.625)10 in IEEE single precision format

(-27.625)10  (11011.101)2
Normalization: 11011.101

M = 101110100000..00,
S EE = 4 + 127 = 131
M  10000011
1 10000011 101110100000..00
1 bit 8 bits 23 bits

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 • 2 standard representations used IEEE 32-bit format
Sign (S) Exponent (E) Mantissa (M)
 Single precision format (32-bit)
1-bit 8-bits 23-bits
IEEE 64-bit format
Sign (S) Exponent (E) Mantissa (M)
Double precision format (64-bit) 1-bit 11-bits 52-bits

n: no. of bits used to store the exponent

IEEE format follows implicit normalization of mantissa

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 Getting the number from IEEE floating point representation

Implicit normalization

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