VLSI CIRCUIT DESIGN PROCESS

VLSI DESIGN FLOW

• DESIGN SPECIFICATION
• DESIGN ENTRY HDL/SCHEMATIC EDITOR
• LOGICAL VERIFICATION
• PLACEMENT,PLANNING AND ROUTING
• TIMING SIMULATION
• FABRICATION
 Stick Diagrams
• VLSI design aims to translate circuit concepts onto
silicon
• stick diagrams are a means of capturing topography
and layer information - simple diagrams
• Stick diagrams convey layer information through
color codes (or monochrome encoding)

ECEA
 Encoding for nMOS process
Stick Encoding Layer Mask Layout Encoding

Thinox

Polysilicon

Metal1

Contact cut

NOT applicable Overglass

Implant

Buried contact

ECEA
 Encoding for pMOS process
Stick Encoding Layer Mask Layout Encoding

P-Diffusion

Not Shown in Stick Diagram P+ Mask

Metl2

VIA

Demarcation Line P-Well

Vdd or GND CONTACT

ECEA
 Stick Diagrams – Notations
Metal 1

poly

ndiff

pdiff
Can also draw
in shades of
CONTACT/VIA gray/line style.

METAL 2

VDD OR VSS CONTACT IMPLANT

6
Stick Diagrams

N+ N+

7
 Stick Diagrams

VDD

x x

Gnd

8
 Stick Diagrams
• VLSI design aims to translate circuit concepts
onto silicon.
• stick diagrams are a means of capturing
topography and layer information using simple
diagrams.
• Stick diagrams convey layer information
through colour codes (or monochrome
encoding).
• Acts as an interface between symbolic circuit
and the actual layout.
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 Stick Diagrams

 Does show all components/vias.

 It shows relative placement of components.
 Goes one step closer to the layout
 Helps plan the layout and routing

A stick diagram is a cartoon of a layout.

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 Stick Diagrams

 Does not show

• Exact placement of components
• Transistor sizes
• Wire lengths, wire widths, tub boundaries.
• Any other low level details such as parasitics..

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 Stick Diagrams – Some rules
Rule 1.
When two or more ‘sticks’ of the same type
cross or touch each other that represents
electrical contact.

12
 Stick Diagrams – Some rules
Rule 2.
When two or more ‘sticks’ of different type cross or
touch each other there is no electrical contact.
(If electrical contact is needed we have to show the connection explicitly).

13
 Stick Diagrams – Some rules
Rule 3.
When a poly crosses diffusion it represents a
transistor.

Note: If a contact is shown then it is not a transistor.

14
 Stick Diagrams – Some rules
Rule 4.
In CMOS a demarcation line is drawn to avoid
touching of p-diff with n-diff. All pMOS must
lie on one side of the line and all nMOS will
have to be on the other side.

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NMOS DESIGN STYLES
• Draw the metal Vdd and Gnd rails in parallel
allowing enough space between other circuit
elements.
• N-diffusion and other thinox regions are drawn with
appropriate contacts.
• Polysilicon crosses n-diffusion paths wherever
transistors are required and implant drawn for
depletion mode transistor.
 NMOS INVERTER STICK DIAGRAM
vdd D

Vo S Vo

D
Vin
Vin

S
Vss
 NMOS NAND
VDD

A
B
 NMOS NOR
VDD
EX-OR
𝑌 = 𝐴 𝐵+ 𝐴 𝐵

𝐴 𝐵+ 𝐴 𝐵

𝐴 𝐵. 𝐴 𝐵
( 𝐴+𝐵)( 𝐴+𝐵)
 NMOS EX-OR
VDD

Y=A ⊕B
 PMOS DESIGN STYLES
• Draw the metal Vdd and Gnd rails in parallel
allowing enough space between other circuit
elements.
• P-diffusion and other thinox regions are drawn
with appropriate contacts.
• Polysilicon crosses P-diffusion paths wherever
transistors are required and implant drawn for
depletion mode transistor.
2 I/P PMOS NAND
2 I/P PMOS NOR
CMOS INVERTER
CMOS NAND
CMOS NOR
CMOS LOGIC FOR
Design rules and Layout
 Design rules and Layout
• Why we use design rules?
– Interface between designer and process engineer
Historically, the process
technology referred to the
length of the silicon channel
between the source and drain
terminals in field effect
transistors (see FET). The sizes
of other features are generally
derived as a ratio of the
channel length, where some
may be larger than the channel
size and some smaller. For
example, in a 90 nm process,
the length of the channel may
be 90 nm, but the width of the
gate terminal may be only 50
nm.
 Design Rules
• Two major approaches:
– “Micron” rules: stated at micron resolution.
–  rules: simplified micron rules with limited
scaling attributes.
• Design rules represents a tolerance which insures
very high probability of correct fabrication
– scalable design rules: lambda parameter
– absolute dimensions (micron rules)
 “Micron” rules
• All minimum sizes and spacing specified in
microns.
• Rules don't have to be multiples of λ.
• Can result in 50% reduction in area over λ
based rules
• Standard in industry.
 Lambda-based Design Rules
• Lambda-based (scalable CMOS) design rules
define scalable rules based on l (which is half
of the minimum channel length)

• Stick diagram is a draft of real layout, it serves

as an abstract view between the schematic
and layout.
• Circuit designer in general want tighter, smaller layouts
for improved performance and decreased silicon area.

• On the other hand, the process engineer wants design

rules that result in a controllable and reproducible
process.

• Generally we find there has to be a compromise for a

competitive circuit to be produced at a reasonable cost.
• All widths, spacing, and distances are written in the
form m

• l = 0.5 X minimum drawn transistor length

 LAYOUT RULES
• These design rules act as a communication link
between circuit designer and process engineer
during the manufacturing phase.
• To avoid short circuits we have to follow some
rules strictly those are of like minimum
spacing, minimum width.
• The layers are having different lengths and
different widths.
 LAYOUT RULES
• Scalable Design rules:
• All rules are defined in terms of single
parameter λ.
• Scaling can be done easily by simply changing
the value of λ
• Lambda Based design rules are the examples
for scalable design rules.
 Absolute design Rules
• Design rules are expressed in absolute dimensions, therefore can
exploit the features of a given process to a maximum degree.
• Scaling & porting is more demanding and has to be performed
manually or using CAD tools.
• A typical minimum for the line width of the diffused active regions
is 3μm and the separation between two active diffused regions is
2.5μm.
• The minimum width for the poly silicon 1 and poly silicon 2 is 2
μm.
• The separation between the poly silicon 1 and poly silicon 1 is 2.5
μm
• The separation between the poly silicon 1 and
2 is 2 μm
• The separation between the poly silicon 2 and
poly silicon 2 is 3 μm
• The minimum line width for the metal 1 is 2.5
μm and metal 2 is 3 μm and the separation
between two metal 1 layers is 2.5 μm ,metal 2
layers is 3 μm
Design Rules
Minimum width of PolySi and diffusion line 2
Minimum width of Metal line 3 as metal lines run over a more uneven
surface than other conducting layers to ensure their continuity

Metal

Diffusion
3

2 2 Polysilicon
Design Rules
PolySi – PolySi space 2
Metal - Metal space 2
Diffusion – Diffusion 3 To avoid the possibility of their associated regions
overlapping and conducting current

Metal
2
Diffusion

2 3 Polysilicon
Design Rules
Diffusion – PolySi  To prevent the lines overlapping to form
unwanted capacitor
Metal lines can pass over both diffusion and polySi without electrical effect.
Where no separation is specified, metal lines can overlap or cross

Metal

Diffusion

 Polysilicon
MASK LAYOUTS and DESIGN RULES
Review - VLSI Levels of Abstraction
Specification
(what the chip does, inputs/outputs)

Architecture
major resources, connections

Register-Transfer
logic blocks, FSMs, connections

Logic
gates, flip-flops, latches, connections

Circuit You are Here

transistors, parasitics, connections

Layout
mask layers, polygons
LAYOUTS
 Why we need design rules
• Masks are tooling for manufacturing.
• Manufacturing processes have inherent
limitations in accuracy.
• Design rules specify geometry of masks which
will provide reasonable yields.
• Design rules are determined by experience.
 Manufacturing problems
• Photoresist shrinkage, tearing.
• Variations in material deposition.
• Variations in temperature.
• Variations in oxide thickness.
• Impurities.
• Variations between lots.
• Variations across a wafer.
 Transistor problems
• Varaiations in threshold voltage:
– oxide thickness;
– ion implanatation;
– poly variations.
• Changes in source/drain diffusion overlap.
• Variations in substrate.
 Wiring problems
• Diffusion: changes in doping -> variations in
resistance, capacitance.
• Poly, metal: variations in height, width ->
variations in resistance, capacitance.
• Shorts and opens:
 Oxide problems
• Variations in height.
• Lack of planarity -> step coverage.

metal 2

metal 2 metal 1
 Via problems
• Via may not be cut all the way through.
• Undesize via has too much resistance.
• Via may be too large and create short.
  and design rules
•  is the size of a minimum feature.
• Specifying  particularizes the scalable rules.
• Parasitics are generally not specified in
units
 Design Rules
• Typical rules:
– Minumum size
– Minimum spacing
– Alignment / overlap
– Composition
– Negative features
 Types of Design Rules
• Scalable Design Rules (e.g. SCMOS)
– Based on scalable “coarse grid” - l (lambda)
– Idea: reduce l value for each new process, but keep rules the
same
• Key advantage: portable layout
• Key disadvantage: not everything scales the same
– Not used in “real life”
• Absolute Design Rules
– Based on absolute distances (e.g. 0.75µm)
– Tuned to a specific process (details usually proprietary)
– Complex, especially for deep submicron
– Layouts not portable
 SCMOS Design Rules
• Intended to be Scalable
– Original rules: SCMOS
– Submicron: SCMOS-SUBM
– Deep Submicron: SCMOS-DEEP
 Design Rules
• Design rules or layout rules provide strict guide lines for
preparing the geographic layouts, which will be used to
configure the actual masks used during fabrication.

• Design rules are the effective interface between the

circuit/system engineer and fabrication engineer.

• The goal of any design rule set is to optimize yield while

keeping the geometry as small as possible without
compromising the reliability of the finished circuit.
 λ( lambda ) - based design rules

• Proposed by Mead and Conway.

• Provides a process and feature size

independent way of setting out mask
dimensions to scale.

• These rules allows for scaling of the designs to

a limited extent, so that the designs are safe
for a longer life time.
 λ( lambda ) - based design rules

• Design rules specify line widths, separations

and extensions in terms of λ.
Design rules for wires (nMOS and CMOS)
Design rules for Transistors
2µ

2µ

2µ 2µ
2µ

2µ

2µ
2µ 1µ 1µ
2µ
2µ 2µ

2µ

2µ
2µ
 Design rules for contacts

The 2 λ X 2 λ contact cut indicates an area in which the oxide

is to be removed down to the underlying polysilicon or diffusion
Surface.
when deposition of the metal layer takes place, the metal
Is deposited through the contact cut areas onto the underlying area
So that contact is made between the layers.
Fig : 3 input NOR gate
 TRANSISTOR DESIGN RULES
Thinox

Metal 1
n-diffusion p-diffusion
3λ
2λ
3λ 3λ
2λ 3λ

Metal 2
2λ
4λ
2λ
2λ 4λ
Polysilicon
4λ
Minimum distance rules between device layers, e.g.,
• polysilicon  metal
• metal  metal
• diffusion  diffusion and
ECEA
• minimum layer overlaps
nMOS transistor mask representation

gate polysilicon

source
drain

metal

Contact holes

diffusion (active
region)

ECEA
 Contact Cuts
• Three possible approaches –
1. Poly to Metal
2. Metal to Diffusion
3. Buried contact (poly to diff) or butting
contact (poly to diff using metal)

ECEA
 Layout Design rules & Lambda ()

2

• Minimize spared diffusion

• Use minimum poly width (2) • Width of contacts = 2
• Multiply contacts

ECEA
 Layout Design rules & Lambda ()

3
6

6

2
2
All device mask dimensions are based on multiples of , e.g., polysilicon minimum
width = 2. Minimum metal to metal spacing = 3
ECEA
 λ (lambda) based design rules - CMOS

• Includes design rules for nMOS and few more

rules unique to well process.
– Ex : in case of N-well CMOS process, N-well, N+ mask and the
special substrate contacts
P-well CMOS design rules
P-well CMOS design rules
CMOS INVERTER
CMOS INVERTER
 ORBIT 2 µm double metal double poly
CMOS / BiCMOS rules

• N – well : brown
• P – well : brown
• Poly 1 : red
• Poly 2 : orange
• n-diffusion or n-active : green
• p-diffusion or p-active : yellow or a
green outline to the yellow
 SCMOS Design Rule Summary
• Line size and spacing:
– metal1: Minimum width=3l, Minimum Spacing=3l
– metal2: Minimum width=3l, Minimum Spacing=4l
– poly: Minimum width= 2l, Minimum Spacing=2l
– ndiff/pdiff: Minimum width= 3l, Minimum Spacing=3l, minimum
ndiff/pdiff seperation=10l
– wells: minimum width=10l,
min distance form well edge to source/drain=5l
• Transistors:
– Min width=3l
– Min length=2l
– Min poly overhang=2l
 SCMOS Design Rule Summary
• Contacts (Vias)
– Cut size: exactly 2l X 2l
– Cut separation: minimum 2l
– Overlap: min 1l in all directions
– Magic approach: Symbolic contact layer min. size 4l X 4l
– Contacts cannot stack (i.e., metal2/metal1/poly)
• Other rules
– cut to poly must be 3l from other poly
– cut to diff must be 3l from other diff
– metal2/metal1 contact cannot be directly over poly
– negative features must be at least 2l in size
– CMP Density rules (AMI/HP subm): 15% Poly, 30% Metal
 Layout Considerations
• Break layout into interconnected cells
• Use hierarchy to control complexity
• Connect cells by
– Abutment
– Added wires
• Key goals:
– Minimize size of overall layout
– Meet performance constraints
– Meet design time deadlines
 Spacings
• Diffusion/diffusion: 3
• Poly/poly: 2
• Poly/diffusion: 1
• Via/via: 2
• Metal1/metal1: 3
• Metal2/metal2: 4
• Metal3/metal3: 4
 Overglass
• Cut in passivation layer.
• Minimum bonding pad: 100 m.
• Pad overlap of glass opening: 6
• Minimum pad spacing to unrelated metal2/3:
30
• Minimum pad spacing to unrelated metal1,
poly, active: 15
1.2 µ DOUBLE METAL SINGLE POLY
INVERTER LAYOUT
TWO INPUT NOR GATE
THREE INPUT NOR GATE
TWO INPUT EXCLUSIVE-OR GATE BY USING
NAND GATE
HALF ADDER
FULL ADDER USING HALF ADDER’s
D-FLIP FLOP