Synthesis

Synthesis : Synthesis is the process of converting technology independent RTL to Technology dependent
Gate level netlist.

Synthesis flow :
Reading input files : The synthesis tool (genus) reads and process these input files to
generate a gate-level-netlist.
And tool uses the information from these files to make optimizations,meet constraints and
produce netlist.
Generic Mapping : The logic netlist mapped to the target tech library.The tech library
includes information about the logic gates and their characteristics.
Logic cell mapping : In this,mapping logical elements in a design in a design described in
HDL, to physical std cells available in target tech library.
Optimization : The synthesized netlist is optimized to meet the design goals like
minimizing power consumption, maximizing performance , reducing area.
Export output files : After completing the synthesis process , we need to export certain
output files that are useful for further process of chip manufacturing .
Inputs and Outputs for Synthesis :

Synthesis
tool

RTL : RTL is an abstraction level of the hardware description language that focuses on
defining how data moves between registers, simulating the operation of digital
circuitry.And these files are saved with “.v” .
Library files : The.lib (library) file contains important information about the electrical
behavior of the standard cells used in the IC design. It includes data such as cell timing
models, power characteristics, voltage thresholds, and other parameters necessary for
accurate timing analysis.
Constraints file : SDC is a short form of “Synopsys Design Constraint”. SDC is a
common format for constraining the design which is supported by almost all Synthesis,
PnR and other tools. Generally, timing, power and area constraints of design are provided
through the SDC file and this file has extension .sdc.
UPF : UPF stands for Unified Power Format.It contains power related information.
Netlist : Netlist is a textual description of a circuit made of components in vlsi design and it
contains all the gate level information and the connection between these gates.

Commands used in Synthesis:

• genus –legacy : Is used to invoke or run the Genus
• set_design <design_name> :This cmnd tells genus which design you are currently
working on,allowing you to perform various operations like synth,opt and analysis of
design.
• Set lib_search_path : This cmnd allows you to specify the directories where Genus
should look for lib when performing synth or design related tasks.
• set hdl_search_path : This command specifies directories where Genus will search for
HDL files during synthesis or other design-related tasks.
• set library_list : This command is essential for defining the libraries containing
standard cells, primitives, and other elements necessary for synth.
• set hdl_file_list : This cmnd used to specify the list of HDL files
• set SDC : Used to specify the constraints for synthesis
• read_hdl : used to read HDL files into design environment.
• elaborate $design : used to elaborate the design,which involves analyzing the design
and building an internal representation of design.
• check_design –unresolved : check_design is used to perform various checks on the
design to ensure correctness and unresolved option is used to specifically check for
unresolved design elements or issues within the design.
• syn_generic : used to set or query synth-related generic parameters.These parameters
affect various aspects of the synth process such as optimization strategies,timing
constraints etc,.
• report_qor : used to generate quality of report.
• report_gates : used to generate a report on the gates used in design.
• report_timing : used to generate a timing report and it displays various timing metrics
such as setup and hold slack,clock freq,and critical paths.
• syn_map : used to map the logical functions described in RTL code to cells in technology
lib to ensure that the design meets area,timing and power constraints.
• syn_opt : used to perform logic optimization.
• write_hdl : This cmnd is helpful if you want to export the synthesized netlist for the
further analysis.
• write_db : cmnd used to write the current design database to a file.
Slack Calculation:

Slack : It is difference between the required times and the actual arrival time for a signal.
Required time (RT) :The time within which data is required to arrive at some internal node
of the design.
RT = Clock period - setup time
Arrival time (AT) : Which is also called as actual time and defined as the time in which data
arrives at the internal node. It incorporates all the net and logic delays in between the
reference input point and the destination node.
AT = Tclk-q + Comb delay
Setup Slack = Required time - Arrival time
Hold slack = Arrival time - Required time
Now checking the Slack in reg to reg path :
After Synthesis, in the timing report (reg2reg) setup =77,Tclk=1200 ,Tclkq=95.
Required time = Tclk – setup = 1200 – 77 = 1123
Arrival time = Tclk-q + Tcomb = 95+1028=1123
Slack = RT – AT = 1123 –1123 = 0
Ibex reports:

syn_generic syn_map syn_opt

area 0.000 5185.659 5045.587
gates 23960 10851 10335
timing(reg2reg) 232.3/0.0/0 217.3/0.0/0 214.8/0.0/0
WNS/TNS/FEP
Synthesis
Design Name ibe x_c ore

Clock Period 1200

Timing (Reg2Reg)
(W NS/TNS/FEP) 0.0/0.0/0.0

Unresolved References 0
Empty Modules 0
Unloaded Port(s) 8
Unloaded Sequential Pin(s) 0
Unloaded Combinational
Pin(s) 0
Undriven Port(s) 0
Undriven Leaf Pin(s) 0
Undriven hierarchical pin(s) 0
Multidriven Port(s) 0
Multidriven Leaf Pin(s) 0
Multidriven hierarchical Pin(s) 0
Multidriven unloaded net(s) 0
Constant Port(s) 6
Constant Leaf Pin(s) 0
Constant hierarchical Pin(s) 0
Preserved leaf instance(s) 0
Preserved hierarchical
instance(s) 0
Feedthrough Modules(s) 0
Libcells with no LEF cell 0
Physical (LEF) cells with no
libcell 0

No. of sequential cells 1926

No. of inverters 909
No. of buffers 20
No. of logic 7480
No. of physical cells 0
Total Number of cells 10335
Area of sequential cells 2430.363
Area of inverters 156.172
Area of buffers 4.303
Area of logic 2454.209
Area of physical cells 0
Total Area 5045.587

Lint report errors 263

Riscv report:

syn_generic syn_map syn_opt

area 12.131 2305.532 2288.218
gates 11884 4687 4647
timing(reg2reg) 118.16/0.0/0 51.7/0.0/0 31.2/0.0/0
WNS/TNS/FEP
Floorplan
Floor planning:
The floorplan stage involves crucial decisions about how to lay out the components on
the chip or core. It determines the physical placement of macros (large functional blocks),
creates the power grid, and defines the placement of input and output (I/O) pins or pads.
Inputs:
• Netlist (.v)
• Technology file (techlef)
• Timing Library files (.lib)
• Physical library (.lef)
• Synopsys design constraints (.sdc)
• Tlu+file
key terms related to floorplan:
core area depends upon :
1.Aspect ratio: Aspect ratio will decide the size and shape of the chip. It is the ratio
between horizontal routing resources to vertical routing resources (or) ratio of height and
width. Aspect ratio = width/height
2.Core utilization:- Utilization will define the area occupied by the standard cells, macros,
and other cells.If core utilization is 0.8 (80%) that means 80% of the core area is used for
placing the standard cells, macros, and other cells, and the remaining 20% is used for
routing purposes.
core utilization = (macros area + std cell area +pads area)/ total core area
3.Macro placement:
Macros may be memories, analog blocks. Proper placement of macros has a great impact on
the quality and performance of the ASIC design. Macro placement can be manual or
automatic.
Manual macro placement is more efficient when there are few macros to be placed. Manual
macro placement is done based on the connectivity information of macros to IO pin/pads
and macro to macro. Automatic macro placement is more appropriate if the number of
macros is large.
Types of macros:
•Hard macros: The circuit is fixed. We can’t see the functionality information about
macros. Only we know the timing information.
Soft macros: The circuit is not fixed and we can see the functionality and which type of
gates are using inside it. Also we know the timing information.
Guidelines to place macros:
•Placement of macros are the based on the fly-lines ( its shows the connectivity b/w macro
to macro and macro to pins) so we can minimize the interconnect length between IO pins
and other cells.
•Place the macros around to the boundary of the core, leaving some space between macro to
core edge so that during optimization this space will be used for buffer/inverter insertion
and keeping large areas for placement of standard cells during the placement stage.
•Macros that are communicating with pins/ports of core place them near to core boundary.
•Place the macros of same hierarchy together.
•Keep the sufficient channel between macros
channel width = (number of pins * pitch )/ number of layers either horizontal or
vertical .
Pitch = width of nets * spacing between the nets
4.Rows: Locations where cells are placed (can be core or IO rows).
5.Sites: The smallest unit of placement (where the smallest cell can fit).
6.Blockages: Define areas where placement is restricted (soft, hard, or partial).
7.Halo/Keepout Margin: Ensures separation between different elements.
Commands used in Floorplan:
set_design <design_name> : This command is used to specify which design (circuit or
layout) you are currently working on or manipulating within the tool.
set lef_file_list : command is used to specify a list of LEF (Library Exchange Format) files
that contain information about the physical properties of standard cell libraries, such as cell
dimensions, pin locations, routing layers, and more.
set synthesis_netlist : command is used to assign this synthesized netlist to a specific
variable or property within the Cadence environment. This allows subsequent tools or
scripts to reference and manipulate the netlist as needed for further design stages, such as
optimization, verification, and physical implementation.
set mmmc_file : command is typically used to specify the location of an MMMC (Mixed
Mode Model Card) file. MMMC files contain information about mixed-signal models used
in a design.
set fp_x & set fp_y : these cmnds are used to set the position of the floorplan origin in
layout design space.
init_design : "init_design" typically refers to the initial setup or initialization of a design
project within the Innovus tool suite for digital IC (Integrated Circuit) design.
floorPlan : command is used to define the initial floorplan for a digital integrated circuit
(IC) design.
creatRow : command is used to create rows of standard cells within the floorplan of a
digital integrated circuit (IC) design.
editPin : command is used to modify the properties of pins within the layout of a digital
integrated circuit (IC) design those are pin name ,direction ,function ,location,size etc,.
legalizePin : command is used to ensure that the placement of pins within the layout of a
digital integrated circuit (IC) design complies with the design rules and constraints.
"Legalizing" pins refers to adjusting their positions or properties to meet the requirements
specified by the design rules, such as minimum spacing, alignment, or clearance.
defOut –floorplan : command is used to generate a DEF (Design Exchange Format) file
containing the physical layout information of the digital integrated circuit (IC) design for
the next step.
Ibex_project floorplan related information:

Before resizing the floorplan for higher utilization value

Core utilization =total core area

occupied/total core area
available
=5045.587/(101.268*99.648)
=0.500 *100
=50%
After resizing the floorplan for higher utilization value

Core utilization =total core area

occupied/total core area available
=5045.587/(85*83)
=0.715 *100
=71.5%
Pin placement at different edges (0,1,2,3) and different layers using “–edge” switch in
editPin command

pin placement at edge 0

editPin -pin $pins -layer {M3 M5} -snap TRACK -spacing 1 -spreadDirection clockwise -pattern fill_track -start {0.0 0.0} -end {0.0 80.0} -edge 0

pin placement at edge 1

editPin -pin $pins -layer {M3 M5} -snap TRACK -spacing 1 -spreadDirection clockwise -pattern fill_track -start {0.0 0.0} -end {0.0 80.0} -edge 1
 Pin placement at edge 2

editPin -pin $pins -layer {M3 M5} -snap TRACK -spacing 1 -spreadDirection clockwise -pattern fill_track -start {0.0 0.0} -end {0.0 80.0} -edge 2

Pin placement at edge 3

editPin -pin $pins -layer {M3 M5} -snap TRACK -spacing 1 -spreadDirection clockwise -pattern fill_track -start {0.0 0.0} -end {0.0 80.0} -edge 3
Pin placement with input pins in one location and output pins in another location
get_ports [all_inputs | all_outputs] --- it will give list of input and output pins
set pin_list_name [get_ports [all_inputs | all_outputs]]
editPin -pin $input_pin_list -layer {M3 M5} -snap TRACK -spacing 1 -spreadDirection clockwise -pattern fill_track -start {0.0 0.0} -end {0.0 80.0} -edge 1 ----- for inputpins
editPin -pin $output_pin_list -layer {M4 M6} -snap TRACK -spacing 1 -spreadDirection clockwise -pattern fill_track -start {0.0 0.0} -end {0.0 80.0} -edge 3 ----- for outputpins
Floorplan outputs :
1.get core and boundary area
2.IO ports/pins placed
3.macros placement done
4.floorplan def file (.def or .fp)
Placement
Placement :
Placement is the process of placing the standard cells inside the core boundary in an optimal
location. The tool tries to place the standard cell in such a way that the design should have
minimal congestions and the best timing.
Placement does not place only the standard cells present in the synthesized netlist but also
places many physical only cells and adds buffers/inverters as per the requirement to meet the
timings, DRV, and foundry requirements. Here are the basic steps which the tool performs
during the placement and optimization stage.
1.Pre Placement
2.Initial Placement / Course Placement / Global Placement
3.Legalization
4.HFNS (Hign Fanout Net Synthesis)
5.Iteration for Congestion, Timing, DRV, and Power Optimization
6.Area recovery
7.Scan-Chain Reorder
8.Tie Cell insertion.
Inputs :
1.Gate-level netlist
2.Floorplan database
3.Constraints file
4.Logical and physical library files.
1.Pre Placement : Before starting the actual placement of the standard cells present in the
synthesized netlist, we need to place various physical only cells like end-cap cells, well-tap
cells, IO buffers, antenna diodes, and spare cells.
2. Initial Placement / Course Placement / Global Placement : In this,the placement tool
determines the approximate locations of each cells according to the timing and congestion.
3.Legalization : During legalization placement,the tool will move the cells to legal locations
to avoid overlap between cells.
4. HFNS (Hign Fanout Net Synthesis) : It is the process of buffering the high fanout nets to
balance the load.
5. Iteration for Congestion, Timing, DRV, and Power Optimization : In this step tool
first, do an early global route and estimate the routing overflow/congestions in the design.
The tool tries to initially minimize the congestion in this stage. Next, the tool starts the RC
extraction to calculate the delay for setup analysis. The tool tries to minimize the setup WNS
and TNS in this step. Similarly, the tool also tries to minimize the DRV and Power in this
stage.Congestion Reduced by using some techniques like Halos or keepout margin ,cell
padding,blockages .
Scan chain re-ordering : Is the process of reconnecting the scan chains to optimize the
routing by re ordering the scan chain connection will improve congetiono and timing.
Tie Cell insertion : There are some unused inputs of logic gates in the netlist which is tied to
either vdd or vss, is not recommended and for that we have tie high and tie low cells in the
library.