CHAPTER 4

BASIC COMPUTER ORGANIZATION

 Chapter4 Basic Computer Organization
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 4.1 Stored program organization

 4.2 Timing and control
 4.3 Instruction cycle
 4.4 Chip Organization
 4.5 I/O and interrupt
 4.1 Stored program organization
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 The von Neumann architecture is a design model

for a stored-program digital computer that uses a
processing unit and a single separate storage
structure to hold both instructions and data.
 A stored-program digital computer is one that
keeps its programmed instructions, as well as its
data, in read-write, random access memory (RAM).
 4.1 Stored program organization
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 4.1 Stored program organization
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 4.2 Timing and control
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 CLOCK
 Activities on the system bus is synchronized by the
system clock
 Activities include:
 Reading from memory or / IO
 Writing to memory /IO
 4.2 Timing and control
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 Clock cycle
 The speed of a computer processor, or CPU, is
determined by the clock cycle.
 The clock speed is measured in Hz, typically either
megahertz (MHz) or gigahertz (GHz).
 For example, a 4GHz processor performs 4,000,000,000
clock cycles per second.
 4.2 Timing and control
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 T-state
 One complete cycle of clock is called as T-state as
shown in the above figure. The time intervals T1T1
orT2T2 are the examples of T-state.
 A T-state is measured from the falling edge of one
clock pulse to the falling edge of the next clock pulse.
 4.2 Timing and control
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 Bus cycle
 Any read or write cycle is called a bus cycle (machine cycle)
 8086 ,a bus cycle takes 4 T states, where one T state is
defined as the ‘period’ of the clock.
 During a machine cycle, one specific operation- reading or
writing is accomplished.
 4 basic machine cycles
 Memory Read
 Memory Write
 I/O Read
 I/O Write
 4.3 Instruction cycle
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 Instruction cycle
 Time taken by processor to execute an instruction- specified
in terms of no. clock cycles needed to do it.
 Once instruction is fetched and ready to be executed, then it
can be decoded and execution can be set.
 Fetch-execute cycle can be divided into 6 stages
 Fetch instruction
 Decode instruction
 Read operand address
 Fetch operand
 Execute instruction
 Write/store result in memory
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 Instruction cycle
 Fetching the instruction
 The next instruction is fetched from the memory
address that is currently stored in the program counter
(PC) and stored in the instruction register (IR).
 At the end of the fetch operation, the PC points to the
next instruction that will be read at the next cycle.
 Decode the instruction
 During this cycle the encoded instruction present in the
IR (instruction register) is interpreted by the decoder.
 4.3 Instruction cycle
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 Instruction cycle
 Read the effective address
 In case of a memory instruction (direct or indirect) the
execution phase will be in the next clock pulse.
 If the instruction has an indirect address, the effective
address is read from main memory and any required data
is fetched from main memory to be processed and then
placed into data registers (Clock Pulse: T3).
 If the instruction is direct, nothing is done at this clock
pulse. If this is an I/O instruction or a Register instruction,
the operation is performed (executed) at clock Pulse.
 4.3 Instruction cycle
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 Instruction cycle
 Execute the instruction
 The control unit of the CPU passes the decoded information as a
sequence of control signals to the relevant function units of the CPU
to perform the actions required by the instruction such as reading
values from registers, passing them to the ALU to perform
mathematical or logic functions on them and writing the result back
to a register.
 If the ALU is involved, it sends a condition signal back to the CU. The
result generated by the operation is stored in the main memory or
sent to an output device.
 Based on the condition of any feedback from the ALU, Program
Counter may be updated to a different address from which the next
instruction will be fetched.
 4.4 Chip Organization
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 Hardware -- Parts of a computer you can touch

 PC/Workstation/Mainframe
 Network
 Software -- Parts of a computer you cannot
touch
 Operating Systems
 Mac OS/Windows/Linux/iOS/Android
 Program
 A set of instructions for a computer to follow.
 4.4 Chip Organization
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 Von Neumann computer model

 Five main components of a computer
 4.4 Chip Organization
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 Von Neumann computer model

 Five main components of a computer
 4.4 Chip Organization
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 CPU (Central processing unit)

 CPU is an electronic circuitry that carries out
the instruction given by a computer program.
 CPU execute instruction by performing basic
arithmetic, logical, control and I/O operations
as required per instruction.
 4.4 Chip Organization
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 Main memory
 Random Access Memory
 Used when running the program
 Secondary memory
 Hard disks, CD/DVD flash drives
 Data storage for permanent record
 4.4 Chip Organization
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 Input devices
 Allows a person communicate information to the
computer
 Keyboard/Mouse/Microphone/Camera
 Output devices
 Allows the computer to communicate information to
you.
 Monitor/Speaker/Printer
 4.4 Chip Organization
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 Software -- Parts of a computer you cannot touch

 Operating Systems
 Mac OS/Windows/Linux/iOS/Android
 Program
 A set of instructions for a computer to follow.
 4.4 Chip Organization
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 Three important terminologies ALU

Microprocessor Register

Control part

Microcomputer Memory (RAM/ROM)

I/O port

Bus (AB, DB, CB)

Hardware
Input device
External
Output device
Peripheral
equipment
Micro-
Power circuit
Computer
Auxiliary part
System
Clock circuit

System software (operation system, compile programmer...)

Software Programming software(machine language, assemble langue)

Application software (data processing, industrial control...)

 4.5 I/O and interrupt
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 Interrupt
 Interrupt is the method of creating a temporary halt
during program execution and allows peripheral
devices to access the microprocessor.
 The microprocessor responds to that interrupt with an
ISR (Interrupt Service Routine), which is a short
program to instruct the microprocessor on how to
handle the interrupt.
 4.5 I/O and interrupt
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 Types of interrupts
 4.5 I/O and interrupt
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 Hardware Interrupts
 Hardware interrupt is caused by any peripheral device
by sending a signal through a specified pin to the
microprocessor.
 The 8086 has two hardware interrupt pins, i.e. NMI
and INTR.
 NMI is a non-maskable interrupt and INTR is a maskable
interrupt having lower priority.
 One more interrupt pin associated is INTA called interrupt
acknowledge.
 4.5 I/O and interrupt
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 NMI
 It is a single non-maskable interrupt pin (NMI) having higher
priority than the maskable interrupt request pin (INTR)and it
is of type 2 interrupt.
 When this interrupt is activated, these actions take place.
 Completes the current instruction that is in progress.
 Pushes the Flag register values on to the stack.
 Pushes the CS (code segment) value and IP (instruction pointer)
value of the return address on to the stack.
 IP is loaded from the contents of the word location 00008H.
 CS is loaded from the contents of the next word location 0000AH.
 Interrupt flag and trap flag are reset to 0.
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 INTR
 The INTR is a maskable interrupt because the microprocessor
will be interrupted only if interrupts are enabled using set
interrupt flag instruction. It should not be enabled using clear
interrupt Flag instruction.
 The INTR interrupt is activated by an I/O port. If the interrupt
is enabled and NMI is disabled, then the microprocessor first
completes the current execution and sends ‘0’ on INTA pin
twice. The first ‘0’ means INTA informs the external device to
get ready and during the second ‘0’ the microprocessor
receives the 8 bit, say X, from the programmable interrupt
controller.
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 INTR
 These actions are taken by the microprocessor
 First completes the current instruction.
 Activates INTA output and receives the interrupt type, say
X.
 Flag register value, CS value of the return address and IP
value of the return address are pushed on to the stack.
 IP value is loaded from the contents of word location X × 4
 CS is loaded from the contents of the next word location.
 Interrupt flag and trap flag is reset to 0