8086 Architecture

Dr. Debashish Dash.

Dept. of Micro & Nano Electronics
VIT University

1
Block diagram of 8086

2
Software Model of the 8086 Microprocessors

3
 8086 Registers
General Purpose Index
AH AL
BP
AX

SP
BH BL
BX
SI

CH CL
DI
CX

DH DL
DX Segment

CS

Status and Control SS

Flags DS

IP ES

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 General Purpose Registers

AX - the Accumulator
BX - the Base Register
CX - the Count Register
DX - the Data Register

• Normally used for storing temporary results

• Each of the registers is 16 bits wide (AX, BX, CX, DX)
• Can be accessed as either 16 or 8 bits AX, AH, AL
5
 General Purpose Registers
• AX
– Accumulator Register
– Preferred register to use in arithmetic, logic and data
transfer instructions because it generates the
shortest Machine Language Code
– Must be used in multiplication and division
operations
– Must also be used in I/O operations

• BX
– Base Register
– Also serves as an address register

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 General Purpose Registers
• CX
– Count register
– Used as a loop counter
– Used in shift and rotate operations

• DX
– Data register
– Used in multiplication and division
– Also used in I/O operations

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 Pointer and Index Registers

• All 16 bits wide, L/H bytes are not accessible

• Used as memory pointers

– Example: MOV AH, [SI]
• Move the byte stored in memory location whose address is contained in
register SI to register AH

• IP is not under direct control of the programmer

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 Flag Register

Overflow Carry
Direction Parity

Interrupt enable Auxiliary Carry

Trap Zero
6 are status flags
Sign
3 are control flag
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 8086 Programmer’s Model
ES Extra Segment
CS Code Segment
BIU registers SS Stack Segment
(20 bit adder)
DS Data Segment
IP Instruction Pointer

AX AH AL Accumulator
EU registers BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
DI Destination Index Register
FLAGS

10
 The Stack
• The stack is used for temporary storage of information
such as data or addresses.

• When a CALL is executed, the 8086 automatically PUSHes

the current value of CS and IP onto the stack.

• Other registers can also be pushed

• Before return from the subroutine, POP instructions can

be used to pop values back from the stack into the
corresponding registers.

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The Stack

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INTEL 8086 - Pin Diagram

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 INTEL 8086 - Pin Details
Power Supply
5V  10%
Ground

Reset
Registers, seg
regs, flags
CS: FFFFH, IP:
0000H
If high for
minimum 4
Clock clks
Duty cycle: 33%
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Duty Cycle

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 INTEL 8086 - Pin Details

Address/Data Bus:
Contains address Address Latch Enable:
bits A15-A0 when ALE
is 1 & data bits D15 – When high,
multiplexed
D0 when ALE is 0.
address/data bus
contains address
information.

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 INTEL 8086 - Pin Details

INTERRUPT

Non - maskable
interrupt

Interrupt
acknowledge

Interrupt request

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INTEL 8086 - Pin Details
Direct
Memory
Access

Hold

Hold
acknowledge

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INTEL 8086 - Pin Details

Address/Status Bus
Address bits A19 –
A16 & Status bits S6 –
S3

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 INTEL 8086 - Pin Details

BHE#, A0: Bus High Enable/S7

0,0: Whole word Enables most
(16-bits)
significant data bits
0,1: High byte D15 – D8 during read
to/from odd address or write operation.
1,0: Low byte S7: Always 1.
to/from even address

1,1: No selection

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 INTEL 8086 - Pin Details

Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V

Minimum Mode Pins

Maximum Mode
Pins

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Minimum Mode- Pin Details

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 Maximum Mode - Pin Details

S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access Status Signal
101: read memory
110: write memory Inputs to 8288 to
111: none -passive generate eliminated
signals due to max
mode.

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 Maximum Mode - Pin Details

Lock Output
Used to lock peripherals
off the system
DMA
Activated by using the Request/Grant
LOCK: prefix on any
instruction

Lock Output

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 Maximum Mode - Pin Details

QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of
opcode
Queue Status
Used by numeric
coprocessor (8087)

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Minimum Mode 8086 System

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Minimum Mode 8086 System

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‘Read’ Cycle timing Diagram for
Minimum Mode

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‘Write’ Cycle timing Diagram for
Minimum Mode

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Maximum Mode 8086 System

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Maximum Mode 8086 System

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 Maximum Mode 8086 System
• Here, either a numeric coprocessor of the type 8087 or another
processor is interfaced with 8086.

• The Memory, Address Bus, Data Buses are shared resources

between the two processors.

• The control signals for Maximum mode of operation are

generated by the Bus Controller chip 8788.

• The three status outputs S0*, S1*, S2* from the processor are
input to 8788.

• The outputs of the bus controller are the Control Signals, namely
DEN, DT/R*, IORC*, IOWTC*, MWTC*, MRDC*, ALE etc.

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Memory Read timing in
Maximum Mode

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Memory Write timing in
Maximum Mode

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8086 Control Signals
1. ALE
2. BHE
3. M/IO
4. DT/R
5. RD
6. WR
7. DEN

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 Coprocessor and Multiprocessor
configuration
• Multiprocessor Systems refer to the use of multiple
processors that executes instructions simultaneously
and communicate with each other using mail boxes and
Semaphores.

• Maximum mode of 8086 is designed to implement 3

basic multiprocessor configurations:
1. Coprocessor (8087)
2. Closely coupled (8089)
3. Loosely coupled (Multibus)
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 Coprocessor and Multiprocessor
configuration
• Coprocessors and Closely coupled configurations are
similar in that both the 8086 and the external processor
shares the:
- Memory
- I/O system
- Bus & bus control logic
- Clock generator

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Coprocessor / Closely Coupled
Configuration

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 TEST pin of 8086
• Used in conjunction with the WAIT instruction in
multiprocessing environments.

• This is input from the 8087 coprocessor.

• During execution of a wait instruction, the CPU checks this

signal.

• If it is low, execution of the signal will continue; if not, it

will stop executing.

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 Advantages of Multiprocessor
Configuration
1. High system throughput can be achieved by having more than
one CPU.
2. The system can be expanded in modular form.
Each bus master module is an independent unit and normally resides on
a separate PC board. One can be added or removed without affecting the
others in the system.
3. A failure in one module normally does not affect the breakdown
of the entire system and the faulty module can be easily
detected and replaced
4. Each bus master has its own local bus to access dedicated
memory or IO devices. So a greater degree of parallel processing
can be achieved.

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 WAIT State
Tw
1 2 3 4
Clock

READY

• A wait state (Tw) is an extra clocking period, inserted

between T2 and T3, to lengthen the bus cycle, allowing
slower memory and I/O components to respond.

• The READY input is sampled at the end of T2, and again,

if necessary in the middle of Tw. If READY is ‘0’ then a
Tw is inserted.
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