1/26

Digital Data Communication Techniques

2/26
Asynchronous and Synchronous
Transmission
Timing problems require a mechanism to
synchronize the transmitter and receiver
timing (rate, duration, spacing) of the data bits must be the
same at transmitter & receiver
receiver samples stream of data bits at bit intervals
if clocks not aligned and drifting, the receiver will sample at
wrong time after sufficient bits are sent
Example: for 1Mbps data stream, one bit will be transmitted
every 1s. With 1% clock drift at the receiver (faster or
slower than transmitter), then wrong sampling will occur
after 50 bit (50*0.01s=0.5 s).
Two solutions to synchronizing clocks
asynchronous transmission
synchronous transmission
3/26
Asynchronous Transmission
Avoid timing problem by not sending long stream of bits
Data is transmitted one character at a time, where each
character is five or eight bits in length
Receiver can synchronize at the beginning of each new
character
idle state: no transmission,
NRZ-L signalling is common for asynchronous transmission
The beginning of the character is signalled by a start bit
This is followed by a character of 5 or 8 bits long
The bits of the character are transmitted beginning with the
least significant bit
A parity bit is then added for the purpose of error detection
The end of the character is a stop element.
4/26
Asynchronous Transmission
5/26
Effect of timing error in asynchronous
transmission
Example: The figure below shows the effects of a timing error of
sufficient magnitude to cause error in reception. In this
example, we assume a data rate of 10Kbps; therefore each bit
is 100s duration. Assume that the receiver is fast by 6%, or
6s per bit time. Thus, the receiver samples the incoming
character every 94s. As we can see, the last sample is
erroneous.
6/26
Asynchronous Transmission- Behavior
simple
cheap
overhead of 2 or 3 bits per char (~20%)
good for data with large gaps (keyboard)
Synchronous Transmission
7/26
Block of data bits are transmitted as a frame
Clocks must be synchronized
can use separate clock line between transmitter & receiver
one side send one short pulse and the other side uses this pulse for
clocking; problem with long distances
or embed the clocking information in the data signal
Manchester encoding for digital signals
carrier frequency for analog transmission
Need to indicate start and end of block of data
use preamble (8bit flag) and postamble (8bit flag)
Control fields contain data link control protocol information
More efficient (lower overhead) than asynchronous
Synchronous Frame format
8/26
More efficient (lower overhead) than asynchronous
transmission (two start and stop bits for every 8 bit character,
(2/(2+8))*100%=20%).
Example: A frame in one of the standard schemes contains 48
bits of control, preamble, and postamble. Thus, for a 1000
character block of data, each frame consists of 48 bits of
overhead and 1000*8=8000 bits of data, for a percentage
overhead of only (48/(8000+48))*100%=0.6%.
Synchronous Transmission
9/26
Types of Errors
An error occurs when a bit is altered between
transmission and reception (1 is transmitted and 0 is
received, and visa versa)
Single bit errors
only one bit altered
caused by white noise
Burst errors
contiguous sequence of B bits in which first, last, and any
number of intermediate bits in error
caused by impulse noise or by fading in wireless
effect greater at higher data rates
Example: An impulse noise event or fading event of 1s occurs. At a
data rate of 10Mbps, there is a resulting error burst of 10 bits. At a data rate
of 100Mbps, there is an error burst of 100bits.
10/26
Error Detection
Define the following probabilities:
P
b
: probability that a bit is received in error, known as Bit Error Rate (BER)
P
1
: probability that a frame arrives with no bit error
P
2
: probability that, with an error detecting algorithm in use, a frame arrives
with one or more undetected errors
P
1
=(1-P
b
)
F
where F is the number of bits per frame
P
2
=1-P
1
Example: a defined objective for the ISDN (Integrated Service Digital
Network) is that the BER on a 64-Kbps channel should be less than 10
-6
.
Suppose that one frame with undetected bit error occur per day, and the
frame length is 1000bits. Determine P
1
and P
2
.

6
1 2
1000 6
1
6
6
2
6
10 18 . 0 001 . 0 999 . 0 1 1 ; 999 . 0 ) 10 1 ( ) 1 (
10 18 . 0
10 5296 . 5
1
10 5296 . 5
1000
1
1
24
1
min 60
min 1
60 64

>> = = = = = =
=

=
=
P P P P
P
frames
bit
frame
day
hour
hour
s
s
Kbit
F
b
11/26
Error Detection
Will have errors
Detect using error-detecting code
This code is added by the transmitter
Recalculated and checked by the receiver
Still chance of undetected errors
Parity
parity bit set so character has even (even parity)
or odd (odd parity) number of ones
even number of bit errors goes undetected
12/26
Error Detection Process
13/26
Parity Check
Example: If the transmitter is transmitting an IRA character G
(1110001) and using an odd parity, it will append a 1 and
transmit 11110001. The receiver examines the received
character and, if the total number of 1s is odd, assumes that no
error has occurred. If one bit (or any odd number of bits) is
erroneously inverted during transmission (for example,
11100001), then the receiver will detect an error.
14/26
Cyclic Redundancy Check (CRC)
CRC is one of most common and powerful error
detection code
for block of k data bits, the transmitter generates an
n-k bit sequence called Frame Check Sequence
(FCS), such as the resulting frame length is n bits
transmits the n bit frame which is exactly divisible by
some number
receiver divides frame by that number
if no remainder, assume no error
for math, see Stallings chapter 6
15/26
Cyclic Redundancy Check (CRC)
CRC can be clarified by three equivalent ways:
Modulo 2 Arithmetic
Polynomials
Digital Logic
Modulo 2 Arithmetic: binary addition with no carry
(exclusive-OR (XOR) operation)
0100
______
1010
1110
+
16/26
CRC: Modulo 2 Arithmetic
Data FCS
D F
T
Q
P
R R
Q
P
R
P
R
Q
P
R
P
D
P
R D
P
T
T/P
R D T
R Q
P
R
Q
P
D
F D T
k n P
T k n k n F
T k k D
n T
Define
n-k n-k
n-k
n-k
n-k
=
+
+ = + + = + =
+
=
+ =
+ =
+ =
+ =
=
=
=
2 2
: remainder no have check that To
2
: then FCS, our as remainder this using By
remainder. the is and quotient the is Where
2
: that Suppose
2
divisor ned predetermi the bits, ) 1 ( of Pattern
of bits ) ( last the FCS, bit ) (
of bits first the data, of block bit
ed transmitt be to frame bit
:
17/26
CRC: Polynomials
A second way of viewing the CRC process is to express all
values as polynomials in a dummy variable X, with binary
coefficients
The coefficients corresponds to the bits in the binary number
1 ) ( 110101
1 ) ( 1010001101
2 4 5
2 3 7 9
+ + + = =
+ + + + = =
X X X X P have we P For
X X X X X D have we D For
) ( ) ( ) ( 2
) (
) (
) (
) (
) ( 2
s Polynomial addition 2 Modulo
X R X D X X T R D T
X P
X R
X Q
X P
X D X
P
R
Q
P
D
n-k n-k
n-k n-k
+ = + =
+ = + =
18/26
CRC: Polynomials
1 ) ( 110101
1 ) ( 1010001101
2 4 5
2 3 7 9
+ + + = =
+ + + + = =
X X X X P have we P For
X X X X X D have we D For
zero to equal is ) ( / of remainder the Check that
) ( ) ( ) ( ) ( ) (
1
) (
) (
) (
) (
) (
) (
2 3 5 7 8 12 14 5
2 4 5
2 3
2 4 6 8 9
X P T(X)
X X X X X X X X X R X D X X T
X X X
X X X
X X X X X X
X P
X R
X Q
X P
X D X
n-k
+ + + + + + + = + =
+ + +
+ +
+ + + + + + = + =
01110 = R
19/26
Error Correction Process
FEC: Forward Error Correction
20/26
Error Correction Process
On the transmission, each k-bit block of data is mapped into an
n-bit block (n > k) called a codeword, using an FEC (Forward
Error Correction) encoder.
At the receiver, the FEC decoder has four possible outcomes:
1. If there are no bit errors, the decoder produces the original
data block as output.
2. For certain error patterns, it is possible for the decoder to
detect and correct those errors
3. For certain error patterns, the decoder can detect but not
correct the errors, the decoder simply reports an uncorrectable
error.
4. For certain, typically rare, error patterns, the decoder does
not detect that any errors have occurred
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Block Code Principles
The Hamming distance d(v
1
, v
2
) between two n-bit binary sequences v
1
and
v
2
is the number of bits in which v
1
and v
2
disagree
If v
1
=011011 and v
2
=110001, the d(v
1
, v
2
)=3
Consider the following assignment:




Suppose that a codeword block is received with the bit pattern 00100. This
is a not valid code word, so an error is detected.
The Hamming distance d(00000, 00100) =1
d(00111, 00100) =2
d(11001, 00100) =4
d(11110, 00100) =3
Data block Codeword
00 00000
01 00111
10 11001
11 11110
Most probably one bit in error (minimum distance): correct 00100 00000
22/26
Block Code Principles
Consider the following assignment:




The Hamming distance between the code words
d(00000, 00111) =3; d(00000, 11001) =3; d(00000, 11110) =4
d(00111, 11001) =4; d(00111, 11110) =3; d(11001, 11110) =3
The minimum hamming distance = d
min
=3

Data block Codeword
00 00000
01 00111
10 11001
11 11110
The maximum number of guaranteed correctable errors per code word is:


The number of errors that can be detected satisfies:
(

=
2
1
min
d
t
1
min
= d t
23/26
Block Code Principles
With an (n , k) block code, there are 2
k
, valid code words and a
total of 2
n
possible codewords
The ratio of the redundant bits to data bits (n-k)/k is called the
redundancy of the code
The ratio of the data bits to the total bits k/n is called the
code rate
20/26
How Coding Improves System Performance
For BER=10
-6
, the coding gain = 2.77dB
25/26
Line Configuration - Topology
Physical arrangement of
stations on medium
point to point - two stations
such as between two routers /
computers
multi point - multiple stations
traditionally mainframe
computer and terminals
now typically a local area
network (LAN)
26/26
Classify data exchange half or full duplex
Half duplex (two-way alternate)
only one station may transmit at a time
requires one data path
Full duplex (two-way simultaneous)
simultaneous transmission and reception between
two stations
requires two data paths
separate media or frequencies used for each direction
Line Configuration Duplex