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Lecture 3 Cont. Top Level View of Computer Function and Interconnection

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13 views

Lecture 3 Cont. Top Level View of Computer Function and Interconnection

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syed.12682
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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William Stallings

Computer Organization
and Architecture
8th Edition
Chapter 3
Cont. Top Level View of Computer Function
and Interconnection
Book by : Computer, Architecture and Organizations, 8th Edition ,William Stalling
Original Slides by : Adrian J Pullin
Top Level View of Computer
Function and Interconnection
Lecture Outcomes
Understanding of:
• Computer Modules
• Computer Interconnection
• Bus Structure
• Bus Arbitration
• PCI
Connecting
Computer Modules
Memory Connection
Input / Output Connection(1)
Input/Output Connection(2)
CPU Connection
BUS INTERCONNECTION
What is a Bus?
Data Bus
Address bus
Control Bus
• Memory write: causes data on the bus to be written into the addressed location.
• Memory read: causes data from the addressed location to be placed on the bus.
• I/O write: causes data on the bus to be output to the addressed I/O port.
• I/O read: causes data from the addressed I/O port to be placed on the bus.
• Transfer ACK: indicates that data have been accepted from or placed on the bus.
• Bus request: indicates that a module needs to gain control of the bus.
• Bus grant: indicates that a requesting module has been granted control of the bus.
• Interrupt request: indicates that an interrupt is pending.
• Interrupt ACK: acknowledges that the pending interrupt has been recognized.
• Clock: is used to synchronize operations.
• Reset: initializes all modules.
Bus Interconnection Scheme
What do buses look like?
• AGP(accelerated graphics port)
• ATA (IDE)(Advanced Technology Attachment)
• EISA (Extended Industry Standard Architecture)
• SATA (serial AT attachment)
• FireWire (IEEE-1394)
• PCI (peripheral component interconnect)
• Thunderbolt
Physical Realization of Bus Architecture
Single Bus Problems
Traditional (ISA) (with cache)
High Performance Bus
Bus Types
• Dedicated
– Separate data & address lines
• Multiplexed
– Shared lines
– Address valid or data valid control line
– Advantage - fewer lines
– Disadvantages
• More complex control
• Ultimate performance
Bus Arbitration
Centralised or Distributed Arbitration
POINT-TO-POINT INTERCONNECT
• Compared to the shared bus, the point-to-point interconnect has lower latency, higher data rate,
and better scalability.
• Intel’s QuickPath Interconnect (QPI)
– Multiple direct connections:
– Layered protocol architecture:
– Packetized data transfer:

• QPI is defined as a four-layer protocol architecture, encompassing


the following layers
Physical: Consists of the actual wires carrying the signals.
Link: Responsible for reliable transmission and flow control.
Routing: Provides the framework for directing packets through the
fabric.
Protocol: The high-level set of rules for exchanging packets of data
between devices.
PCI Bus
The peripheral component interconnect (PCI) is a popular
high-bandwidth, processor- independent bus that can function as
a mezzanine or peripheral bus. Compared with other common
bus specifications, PCI delivers better system performance for
high-speed I/O subsystems (e.g., graphic display adapters, net-
work interface controllers, and disk controllers).

PCI Express (PCIe) as with QPI, is a point-to-point interconnect


scheme intended to replace bus-based schemes such as PCI.
PCIe Bus Lines (required)
• A key requirement for PCIe is high capacity to support the
needs of higher data rate I/O devices, such as Gigabit Eth-
ernet. Another requirement deals with the need to support
time-dependent data streams.
PCI Physical and Logical Architecture

• Switch: The switch manages multiple PCIe streams.


• PCIe endpoint: An I/O device or controller that imple-
ments PCIe, such as a Gigabit ethernet switch, a graphics or
video controller, disk interface, or a communications con-
troller.
• Legacy endpoint: Legacy endpoint category is intended
for existing designs that have been migrated to PCI Ex-
press, and it allows legacy behaviors such as use of I/O
space and locked transactions.
• PCIe/PCI bridge: Allows older PCI devices to be con-
nected to PCIe-based systems.
PCIe
• As with QPI, PCIe interactions are defined using a protocol architecture. The PCIe pro-
tocol architecture encompasses the following layers
PCI TLP transaction type
Review Questions
 What is the benefit of using a multiple-bus architecture compared to a single-
bus architecture?
List and briefly define the functional groups of signal lines for PCI.
Thank you

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