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Week 11 B

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10 views26 pages

Week 11 B

Uploaded by

Gqgqg
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Lecture 19

Performance Optimization

Xuan ‘Silvia’ Zhang


Washington University in St. Louis

http://classes.engineering.wustl.edu/ese461/
Project FAQ

• Correction
– typo in optical flow: Iy(i, j) = I1(i, j+1) – I1(i, j-1)
– I1(i, j+1) might not exist
• Mid-project report
– behavioral Verilog code and testbench
– show proof of working functional simulation
– ensure synthesizable codes
• Use of external memory
– instantiate in the test bench
– used for large data array or buffers

2
Arrays, Vectors, and Memories

3
Useful Verilog Features

• Display tasks
– $display, $displayb (h, o) in binary, hex, and octal
– $write, $strobe, $monitor
• File I/O tasks
– $fopen, $fclose
– $fdisplay, $fwrite, $fstrobe, $fmonitor
– $readmemb, $readmemh: read a text file into memory

4
Module Partitioning

• Where possible, register module outputs and


keep critical path in one block
• Design Registering
– pipelining
– restructure a long data path with several levels of logic
and break it up over multiple cycles

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Pipelining

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Pipelining

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Adding Structure

• Control the structure by using separate


assignment and parentheses
• Example
– 32-bit arithmetic shift right
– design 1

– design 2

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32-Bit Arithmetic Shift Right

• Design 3

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32-Bit Arithmetic Shift Right

• Optimal structured design

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32-Bit Arithmetic Shift Right

• Without specifying the mux instantiations

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Horizontal Partitioning

• Break circuit into horizontal slices to minimize


maximum fan-in
• Example
– carry lookahead adder:
32-bit adder broken to eight 4-bit blocks
– 32-bit priority encoder

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32-Bit Priority Encoder

• Restructured with four 8-bit blocks

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Priority-Encoded Logic vs Balanced Logic

• If-Then-Else vs Case Statement


– redundant priority

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Hierarchy

• Collapse hierarchy (flattening)


– more efficient synthesis
• Add Hierarchy
– benefit results from structure preservation
– example: 32-bit decoder

– least-efficient implementation

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32-Bit Decoder

• More concise representation

• A balanced tree decoder is even better

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32-Bit Balanced-Tree Decoder

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Performing Operations in Parallel

• Example
– linear search

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Performing Operations in Parallel

• Example
– binary search

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Performing Operations in Parallel

• Example
– parallel search

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MUX for Conditional Assignment

• Example: counter

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MUX for Conditional Assignment

• Example: counter

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Replication

• Large fanout
– manual register duplication to reduce congestion

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Resource Sharing

• Optimize area but hurt speed


– with resource sharing

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Resource Sharing

• Optimize area but hurt speed


– without resource sharing

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Questions?

Comments?

Discussion?

26

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