Chapter 4

Programmable Logic Devices:

CPLDs and FPGAs with
VHDL Design

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 Objectives

 You should be able to:

 Explain the benefits of using PLDs.

 Describe the PLD design flow.

 Understand the differences among PAL,

PLA, SPLD, CPLD, FPGA, and ASIC.

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 Objectives

(Continued)
 Explain how a graphic editor and a VHDL
text editor are used to define logic to a PLD.
 Interpret the output of a simulation file to
describe logic operations.
 Interpret VHDL code for the basic logic
gates.

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 PLD Design Flow

 PLD (Programmable Logic Device)

 Contains thousands of basic logic gates in a single
package
 Capable of performing advanced sequential
functions
 Must be configured to perform a specific function

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 PLD Design Flow
 Computer-aided design (CAD) is used to draw
the schematic.
 Schematic Capture converts to a binary file.
 Program uses the file to alter PLD internal
connections, implementing the desired function.
 VHDL - VHSIC Hardware Description
Language
 VHSIC - Very High Speed Integrated Circuit

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 PLD Design Flow
 Define the problem
 Develop the equations
 Enter the design
 Simulate the input/output
conditions
 Program the PLD
 Test the final programmed
PLD
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 PLD Design Flow

Implementing the equation X = AB + B + C using

7400-series logic ICs
 See Figure 4-3
 Implementing the same equation using a PLD
 See Figure 4-4

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 PLD Design Flow

Implementing the equation X = AB + B + C using

a PLD.

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 PLD Architecture
 SPLD (Simple Programmable Logic Device)
 Four basic types: SPLDs, CPLDs, FPGAs, and
ASICs
 Most basic and least expensive
 Configurable logic gates
 Programmable interconnection points
 Memory flip-flops
 Typically 16 inputs plus complements and10 outputs
 AND gate outputs called product terms

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 PLD Architecture
 PAL (Programmable Array Logic)
 Gives sum-of-products form
 Uses fixed-input OR gates

 PLA (Programmable Logic Array)

 Gives sum-of-products form
 Uses programmable-input OR gates

 Flip-flop memory section

 Data steering circuitry

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 PLD Architecture
 PAL16L8 is a typical PAL device
 The number 16 means 16 inputs

 The number 8 means 8 outputs

 The letter L means outputs are active

LOW

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 PLD Architecture
 CPLD (Complex Programmable Logic
Device)
 Combines several PAL-type SPLDs into a single
package
 Nonvolatile – memory is not lost when power is
removed
 Can be repeatedly programmed to implement
different functions

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 PLD Architecture
 FPGA (Field-Programmable Gate Array)
 Uses a look-up table (LUT) – a truth table listing
all possible input/output combinations.
 More dense and faster than CPLDs

 Volatile – programming is lost when power is

removed.
 Must be reprogrammed each time power is applied
 The Altera Cyclone series is a good example

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 PLD Architecture
 ASIC stands for application-specific integrated
circuit.
 Used for large quantity demand
 After testing on FPGA design is transferred to
ASIC.
 Nonvolatile so programming not lost when power
is removed.
 Can be pin compatible with FPGA

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Using PLDs to Solve Basic Logic
Designs
 Schematic editor
 Connect pre-defined logic symbols
 VHDL editor
 Define the logic
 Compiler
 Language and symbol translation program
 Waveform simulator
 To check the logic operation

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 Using PLDs to Solve Basic Logic
Designs
 Flow of operations
to design, simulate,
and program an
FPGA.

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 Using PLDs to Solve Basic Logic
Designs
 Screen display of a block editor file generated by
Quartus II software for a two-input AND gate.
 Inputs, outputs, and circuit logic are defined simply by
drawing the diagram

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 Using PLDs to Solve Basic Logic
Designs
 Screen display of a VHDL text editor file for a
two-input AND gate.
 Divided into library declaration, entity declaration,
and architecture body.

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 Using PLDs to Solve Basic Logic
Designs
 Screen display of a Quartus II simulation
waveform file for a two-input AND gate.

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 Altera’s Quartus II Tutorial
 Start the Quartus II software and prepare to
implement the Boolean equation X = AB +CD.
 Altera’s Quartus II Tutorial
 Create a new project

 Create a block design file (bdf)

 Draw the digital logic for the Boolean

equation
 Make the circuit connections

 Compile the project

 Altera’s Quartus II Tutorial
 Create a vector waveform file (vwf)

 Add inputs and outputs to the waveform

display
 Create timing waveforms for the inputs

 Perform a functional simulation of the x-

output
 Altera’s Quartus II Tutorial
 Use the Altera development and
education board to program an FPGA.
 Assign pins

 Recompile the project

 Program the FPGA

 Test the logic

 Use the VHDL text editor to recreate

the design used in the block design.
 Summary
 Programmable Logic Devices can be used to
replace 7400-series and 4000-series ICs. They
contain the equivalent of thousands of logic
gates. Computer-Aided Design (CAD) tools
are used to configure them to implement the
desired logic.

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 Summary
 The two most common methods of PLD
design entry are schematic entry and VHDL
entry. To use schematic entry the designer
uses CAD tools to draw the logic that needs to
be implemented. To use VHDL entry the
designer uses a text editor to write program
descriptions defining the logic to be
implemented.

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 Summary
 PLD design software usually includes a logic
simulator. This feature allows the user to
simulate levels to be input to the PLD and shows
the output simulation to those input conditions.
 Most PLDs are erasable and reprogrammable.
This allows the user to test many versions of their
logic design without ever changing ICs.

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 Summary
 Basically there are four types of PLDs:
SPLDs, CPLDs, FPGAs, and ASICs.
 SPLDs use the PAL or PLA architecture.
 They consist of several multi-input AND
gates whose inputs feed the inputs to OR
gates and memory flip-flops.

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 Summary
 The CPLD consists of several
interconnected SPLDs.
 The FPGA is the most dense form of
PLD. It uses a look-up table to determine
the desired output.
 ASICs are equivalent to FPGAs but their
logic is hard-coded.

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