System Design Using FPGA

Presented By:

Asst. Prof. S.Syed Ameer Abbas

Asst. Prof. A.Kamaraj
Asst. Prof. C.Kalyana Sundaram

Date: 25th October, 2012

Technomeet on
Techknowledge Updation
Department of Electronics and Communication Engineering,
Mepco Schlenk Engineering College, Sivakasi
System Design Using FPGA 1
 Outline

 Introduction to ASIC design: What is FPGA?

 Xilinx FPGA
 Xilinx ISE Design flow
 VHDL Programming
 Embedded System Design: Soft-processors MicroBlaze and
PicoBlaze
 Xilinx Platform Studio Design Flow using MicroBlaze
 Xilinx ISE Embedded System Design flow using PicoBlaze
Two Demonstrations

System Design Using FPGA 2

 World of Integrated Circuits
Integrated Circuits

Full-Custom Semi-Custom User

ASICs ASICs Programmable

PLD FPGA

PAL PLA PML LUT MUX Gates

(Look-Up Table)

3 System Design Using FPGA

 Two competing implementation
approaches
ASIC FPGA
Application Specific Field Programmable
Integrated Circuit Gate Array

• designed all the way • no physical layout design;

from behavioral description design ends with
to physical layout a bitstream used
to configure a device
• designs must be sent
• bought off the shelf
for expensive and time
and reconfigured by
consuming fabrication
designers themselves
in semiconductor foundry

4 System Design Using FPGA

 FPGAs vs. ASICs

ASICs FPGAs

Off-the-shelf
High performance
Low development costs
Low power
Short time to the market
Low cost (but only
in high volumes) Reconfigurability

5 System Design Using FPGA

 How can we make a “programmable logic”?

One time programmable

Fuses (destroy internal links with current)
Anti-fuses (grow internal links)
PROM
Reprogrammable
EPROM
EEPROM
Flash
SRAM - volatile

6 System Design Using FPGA

 Major FPGA Vendors
SRAM-based FPGAs
Xilinx, Inc.
Altera Corp.
Atmel
Lattice Semiconductor

Flash & antifuse FPGAs

Actel Corp.
Quick Logic Corp.

7 System Design Using FPGA

Field Programmable Gate Arrays FPGA

Field Programmable Gate Array

‘Simple’ Programmable Logic Blocks
Massive Fabric of Programmable Interconnects
Standard CMOS Integrated Circuit fabrication process as
for memory chips (Moore’s Law)

8 System Design Using FPGA

 What is an FPGA?

9 System Design Using FPGA

 What is an FPGA?

Configurable
Logic
Block RAMs

Block RAMs
Blocks

I/O
Blocks

Block
RAMs

10 System Design Using FPGA

Field Programmable Gate Arrays FPGA

Field Programmable Gate Array

‘Simple’ Programmable Logic Blocks
Massive Fabric of Programmable Interconnects
Standard CMOS Integrated Circuit fabrication process as
for SRAM memory chips (Moore’s Law)

Huge Density of Logic Block ‘Islands’

1,000 … 100,000’s
in a ‘Sea’ of Interconnects

11 System Design Using FPGA

 Field Programmable Gate Arrays FPGA

12 System Design Using FPGA

 Logic Blocks

 Logic Functions implemented in Look Up Table LUTs.

 Flip-Flops. Registers. Clocked Storage elements.
 Multiplexers (select 1 of N inputs)

16-bit SR
16x1 RAM

a 4-input
LUT
b
y
c
mux
d flip-flop
q
e
clock
clock enable
set/reset

13 System Design Using FPGA

 Look Up Tables LUTs

 LUT contains Memory Cells to implement small logic

functions
 Each cell holds ‘0’ or ‘1’ .
 Programmed with outputs of Truth Table
 Inputs select content of one of the cells as output

16-bit SR
16x1 RAM

a 4-input
LUT
b
y
c
mux
d flip-flop
q
e
clock
clock enable
set/reset
Static Random Access Memory
SRAM cells

14 System Design Using FPGA

  Larger Logic Functions built up by connecting many
Logic Blocks together
 Determined by SRAM cells
SRAM

15 System Design Using FPGA

 Dedicated Expansion Multiplexers

 MUXF5 combines 2 LUTs to create

CLB
Any 5-input function (LUT5)
Slice
Or selected functions up to 9 inputs
LUT MUXF6
Or 4x1 multiplexer
 MUXF6 combines 2 slices to form LUT
MUXF5
Any 6-input function (LUT6)
Slice
Or selected functions up to 19 inputs
8x1 multiplexer LUT

 Dedicated muxes are faster and more space LUT

MUXF5
efficient

16 System Design Using FPGA

 Distributed RAM
RAM16X1S
D
WE

=
WCLK
LUT A0 O
A1
A2

 CLB LUT configurable as A3

RAM32X1S
Distributed RAM D
WE

 A LUT equals 16x1 RAM WCLK

A0 O
A1

 Implements Single and Dual- A2

A3
A4

Ports
 Cascade LUTs to increase RAM
LUT
or RAM16X2S
D0
D1
WE

size = WCLK
A0
A1
O0
O1
RAM16X1D
D

 Synchronous write A2
A3
WE
WCLK

or
A0 SPO
 Synchronous/Asynchronous read LUT
A1
A2
 Accompanying flip-flops used for A3
DPRA0 DPO

synchronous read DPRA1

DPRA2
DPRA3

17 System Design Using FPGA

 Shift Register

LUT
IN D Q
 Each LUT can be configured as CE CE

CLK
shift register
 Serial in, serial out D Q
CE
 Dynamically addressable delay
up to 16 cycles
 For programmable pipeline
LUT
= D
CE
Q OUT

 Cascade for greater cycle

delays
 Use CLB flip-flops to add
D Q
depth CE

DEPTH[3:0]

18 System Design Using FPGA

 Block RAM

Port A

Port B
Spartan-II
True Dual-Port
Block RAM

Block RAM

Most efficient memory implementation

Dedicated blocks of memory
Ideal for most memory requirements
4 to 14 memory blocks
 4096 bits per blocks
Use multiple blocks for larger memories
Builds both single and true dual-port RAMs

19 System Design Using FPGA

 Routing Resources

CLB CLB CLB

PSM PSM
Programmable
Switch
CLB CLB CLB Matrix

PSM PSM

CLB CLB CLB

20 System Design Using FPGA

 Clock Distribution

21 System Design Using FPGA

 FPGA Nomenclature

22 System Design Using FPGA

 Advance architecture on modern
FPGAs
Additional components
RAM blocks
Dedicated multipliers
Tri-state buffers
Transceivers
Processor cores
DSP blocks

23 System Design Using FPGA

 Dedicate Arithmetic Blocks

Xilinx

Altera

24 System Design Using FPGA

 Processor Cores

25 System Design Using FPGA

 Input Output I/O Getting data in and out

1 0

2 7

General-purpose I/O
banks 0 through 7

3 6

4 5

Transceiver block
Differential pairs

FPGA

26 System Design Using FPGA

 FPGA Design Flow

27 System Design Using FPGA

 Design flow (1)

Design and implement a simple unit permitting to

Specification (Lab Experiments)

speed up encryption with RC5-similar cipher with
fixed key set on 8031 microcontroller. Unlike in
the experiment 5, this time your unit has to be able
to perform an encryption algorithm by itself,
executing 32 rounds…..

VHDL description (Your Source Files)

Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity RC5_core is
Functional simulation
port(
clock, reset, encr_decr: in std_logic;
data_input: in std_logic_vector(31 downto 0);
data_output: out std_logic_vector(31 downto 0);
out_full: in std_logic;
key_input: in std_logic_vector(31 downto 0);
key_read: out std_logic;
);
end AES_core;

Synthesis
Post-synthesis simulation

28 System Design Using FPGA

 Design flow (2)

Implementation
Timing simulation

Configuration
On chip testing

29 System Design Using FPGA

 Tools used in FPGA Design Flow
Functionally
verified
VHDL code Design
Design

VHDL code

Synplicity
Synplicity Synthesis
Synthesis
Xilinx
XilinxXST
XST
Synplify
SynplifyPro
Pro

Netlist

Implementation
Implementation
Xilinx
XilinxISE
ISE
30 System Design Using FPGA
Bitstream
 Synthesis

31 System Design Using FPGA

 Synthesis Tools

Synplify Pro Xilinx XST

… and others

32 System Design Using FPGA

 Logic Synthesis
VHDL description Circuit netlist
architecture MLU_DATAFLOW of MLU is

signal A1:STD_LOGIC;
signal B1:STD_LOGIC;
signal Y1:STD_LOGIC;
signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;

begin
A1<=A when (NEG_A='0') else
not A;
B1<=B when (NEG_B='0') else
not B;
Y<=Y1 when (NEG_Y='0') else
not Y1;

MUX_0<=A1 and B1;

MUX_1<=A1 or B1;
MUX_2<=A1 xor B1;
MUX_3<=A1 xnor B1;

with (L1 & L0) select

Y1<=MUX_0 when "00",
MUX_1 when "01",
MUX_2 when "10",
MUX_3 when others;

end MLU_DATAFLOW;

33 System Design Using FPGA

 Circuit netlist (RTL view)

34 System Design Using FPGA

 Mapping

LUT0
LUT4

LUT1
FF1
LUT5

LUT2

FF2
LUT3

35 System Design Using FPGA

 Implementation

36 System Design Using FPGA

 Implementation

• After synthesis the entire implementation

process is performed by FPGA vendor tools

37 System Design Using FPGA

38 System Design Using FPGA
 Translation
Synthesis

Circuit netlist Timing Constraints

Native Constraint Editor
Electronic Design or Text Editor
Interchange Format Constraint
File
EDIF NCF UCF User Constraint File

Translation

NGD Native Generic Database file

39 System Design Using FPGA
 Pin Assignment

B10
FPGA P10

SEGMENTS(0)
CLOCK SEGMENTS(1)
H3 CONTROL(0) SEGMENTS(2)
SEGMENTS(3)
CONTROL(1)
CONTROL(2)
LAB2 SEGMENTS(4)
H2

RESET SEGMENTS(5)
K2 SEGMENTS(6) H6
G5
H5
K3
H1
K4

G4

40 System Design Using FPGA

 Mapping

LUT0
LUT4

LUT1
FF1
LUT5

LUT2

FF2
LUT3

41 System Design Using FPGA

 FPGA
Placing
CLB SLICES

42 System Design Using FPGA

 FPGA
Routing
Programmable Connections

43 System Design Using FPGA

 Configuration
• Once a design is implemented, you must create a file
that the FPGA can understand
• This file is called a bit stream: a BIT file (.bit extension)

• The BIT file can be downloaded directly to the FPGA,

or can be converted into a PROM file which stores the
programming information

44 System Design Using FPGA

 -
Bitstrea
m
Configure

generatio
n
-
Implementation

Burning
device
- Placement of
generated netlist onto
Two main stages of the

the device
FPGA Design Flow

- Choosing best
Place & Route

interconnect structure
for the placed design
Technology
dependent

- Application of
“physical constraints”
- Mapping of extracted
logic structures to
device primitives
- Technology dependent
optimization
- Application of
“synthesis constraints”
- Netlist generation

Map
- Creation of
Synthesis

System Design Using FPGA

“Technology View”
- Code analysis
- Derivation of

Synthesis
main logic

independent
Technology
constructions

RTL
- Technology
independent
optimization
- Creation of

45
“RTL View”
 Major FPGA Vendors

• Xilinx, Inc.
Share about 90% of the market
• Altera Corp.
• Atmel
• Lattice Semiconductor
Actel Corp.
• Quick Logic Corp.

46 System Design Using FPGA

 Xilinx FPGA Families
• Old families
• XC3000, XC4000, XC5200
• Old 0.5µm, 0.35µm and 0.25µm technology. Not recommended for modern
designs.
• High-performance families
• Virtex (220 nm)
• Virtex-E, Virtex-EM (180 nm)
• Virtex-II (130 nm)
• Virtex-II PRO (130 nm)
• Virtex-4 (90 nm)
• Virtex-5 (65 nm)
• Virtex-6 (40 nm)
Low Cost Family
• Spartan/XL – derived from XC4000
• Spartan-II – derived from Virtex
• Spartan-IIE – derived from Virtex-E
• Spartan-3 (90 nm)
• Spartan-3E (90 nm) – logic optimized
• Spartan-3A (90 nm) – I/O optimized
• Spartan-3AN (90 nm) – non-volatile,
• Spartan-3A DSP (90 nm) – DSP optimized
• Spartan-6 (45 nm)

47 System Design Using FPGA

 Introduction to VHDL

48 System Design Using FPGA

 VHDL

• VHDL is a language for describing digital

hardware used by industry worldwide

• VHDL is an acronym for VHSIC (Very High

Speed Integrated Circuit) Hardware Description
Language

49 System Design Using FPGA

 VHDL for Specification

VHDL for Simulation

VHDL for Synthesis

50 System Design Using FPGA

 Levels of design description

Algorithmic level
Level of description
Register Transfer Level
most suitable for synthesis
Logic (gate) level

Circuit (transistor) level

Physical (layout) level

51 System Design Using FPGA

 VHDL Design Styles

VHDL Design
Styles
• Testbenches

dataflow structural behavioral

Concurrent Components and Sequential statements

statements interconnects • Registers, counters, etc.
• State machines

Subset most suitable for synthesis

52 System Design Using FPGA

 Example VHDL Code

3 sections to a piece of VHDL code

File extension for a VHDL file is .vhd

Name of the file should be the same as the entity name
(nand_gate.vhd) [OpenCores Coding Guidelines]
LIBRARY ieee;
USE ieee.std_logic_1164.all; LIBRARY
DECLARATION
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
ENTITY DECLARATION
z : OUT STD_LOGIC);
END nand_gate;

ARCHITECTURE model OF nand_gate

IS
ARCHITECTURE BODY
BEGIN
z <= a NAND b;
END model;

53 System Design Using FPGA

 Design Entity
design entity

entity declaration Design Entity - most basic building

block of a design.

architecture 1
One entity can have many different
architectures.
architecture 2

architecture 3

54 System Design Using FPGA

 Entity Declaration

Entity Declaration describes the interface of the
component, i.e. input and output ports.

Entity name Port names Port type

Semicolon
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
No Semicolon
z : OUT STD_LOGIC after last port
);
END nand_gate;

Reserved words Port modes (data flow directions)

55 System Design Using FPGA

 Port Modes - Summary
The Port Mode of the interface describes the direction in which data travels with
respect to the component


In: Data comes into this port and can only be read within the entity. It
can appear only on the right side of a signal or variable assignment.


Out: The value of an output port can only be updated within the entity.
It cannot be read. It can only appear on the left side of a signal
assignment.


Inout: The value of a bi-directional port can be read and updated within
the entity model. It can appear on both sides of a signal assignment.


Buffer: Used for a signal that is an output from an entity. The value of
the signal can be used inside the entity, which means that in an
assignment statement the signal can appear on the left and right sides of
the <= operator. Not recommended to be used in the synthesizable code.

56 System Design Using FPGA

 Architecture (Architecture body)

Describes an implementation of a design entity

Architecture example:

ARCHITECTURE model OF nand_gate IS

BEGIN
z <= a NAND b;
END model;

57 System Design Using FPGA

 Entity Declaration & Architecture
nand_gate.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;

ARCHITECTURE dataflow OF nand_gate IS

BEGIN
z <= a NAND b;
END dataflow;

58 System Design Using FPGA

 STD_LOGIC type demystified
Valu Meaning
e
‘X’ Forcing (Strong driven) Unknown

‘0’ Forcing (Strong driven) 0

‘1’ Forcing (Strong driven) 1

‘Z’ High Impedance

‘W’ Weak (Weakly driven) Unknown

‘L’ Weak (Weakly driven) 0.

Models a pull down.

‘H’ Weak (Weakly driven) 1.

Models a pull up.

‘-’ Don't Care

59 System Design Using FPGA

xor3 Example

60 System Design Using FPGA

 Entity xor3_gate
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY xor3_gate IS
PORT(
A : IN STD_LOGIC;
B : IN STD_LOGIC;
C : IN STD_LOGIC;
Result : OUT STD_LOGIC
);
end xor3_gate;

61 System Design Using FPGA

 Dataflow Architecture (xor3_gate)
ARCHITECTURE dataflow OF xor3_gate IS
SIGNAL U1_OUT: STD_LOGIC;
BEGIN
U1_OUT <= A XOR B;
Result <= U1_OUT XOR C;
END dataflow;

U1_OUT

62 System Design Using FPGA

 Dataflow Description
Describes how data moves through the system and the various processing steps.
Dataflow uses series of concurrent statements to realize logic.
Dataflow is most useful style when series of Boolean equations can represent a
logic  used to implement simple combinational logic
Dataflow code also called “concurrent” code
Concurrent statements are evaluated at the same time; thus, the order of these
statements doesn’t matter
This is not true for sequential/behavioral statements

This order…
U1_out <= A XOR B;
Result <= U1_out XOR C;
Is the same as this order…
Result <= U1_out XOR C;
U1_out <= A XOR B;

63 System Design Using FPGA

 Structural Description
Structural design is the simplest to understand. This style
is the closest to schematic capture and utilizes simple
building blocks to compose logic functions.
Components are interconnected in a hierarchical manner.
Structural descriptions may connect simple gates or
complex, abstract components.
Structural style is useful when expressing a design that is
naturally composed of sub-blocks.

ECE 448 – FPGA and ASIC Design with VHDL

64 System Design Using FPGA

 Behavioral Architecture (xor3 gate)
ARCHITECTURE behavioral OF xor3 IS
BEGIN
xor3_behave: PROCESS (A, B, C)
BEGIN
IF ((A XOR B XOR C) = '1') THEN
Result <= '1';
ELSE
Result <= '0';
END IF;
END PROCESS xor3_behave;
END behavioral;

65 System Design Using FPGA

 Behavioral Description
It accurately models what happens on the inputs and
outputs of the black box (no matter what is inside and how
it works).
This style uses PROCESS statements in VHDL.

66 System Design Using FPGA

 Modeling Wires and Buses

67 System Design Using FPGA

 Data-flow VHDL: Example

x
y s
cin

cout

68 System Design Using FPGA

 Data-flow VHDL: Example (1)

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY fulladd IS
PORT ( x : IN STD_LOGIC ;
y : IN STD_LOGIC ;
cin : IN STD_LOGIC ;
s : OUT STD_LOGIC ;
cout : OUT STD_LOGIC ) ;
END fulladd ;

69 System Design Using FPGA

 Data-flow VHDL: Example (2)

ARCHITECTURE dataflow OF fulladd IS

BEGIN
s <= x XOR y XOR cin ;
cout <= (x AND y) OR (cin AND x) OR (cin AND y) ;
END dataflow ;

70 System Design Using FPGA

Logic Operators

• Logic operators
and or nand nor xor not xnor

• Logic operators precedence

only in VHDL-93
Highest
not
and or nand nor xor xnor
Lowest

71 System Design Using FPGA

 Multiplexers

72 System Design Using FPGA

 2-to-1 Multiplexer

s
s f

w
0 0 w
f 0 0
w
1 1 1 w
1

(a) Graphical symbol (b) Truth table

73 System Design Using FPGA

 VHDL code for a 2-to-1 Multiplexer

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY mux2to1 IS
PORT ( w0, w1, s : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END mux2to1 ;

ARCHITECTURE dataflow OF mux2to1 IS

BEGIN
f <= w0 WHEN s = '0' ELSE w1 ;
END dataflow ;

74 System Design Using FPGA

 Cascade of two multiplexers

w 0
3
0
w 1 y
2 w
1 1

s2
s1

75 System Design Using FPGA

 VHDL code for a cascade of
two multiplexers
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY mux_cascade IS
PORT ( w1, w2, w3: IN STD_LOGIC ;
s1, s2 : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END mux_cascade ;

ARCHITECTURE dataflow OF mux2to1 IS

BEGIN
f <= w1 WHEN s1 = ‘1' ELSE
w2 WHEN s2 = ‘1’ ELSE
w3 ;
END dataflow ;
76 System Design Using FPGA
Operators

• Relational operators
= /= < <= > >=

• Logic and relational operators precedence

Highest not
= /= < <= > >=
Lowest and or nand nor xor xnor

77 System Design Using FPGA

 VHDL operators

78 System Design Using FPGA

 VHDL code for a 4-to-1 Multiplexer
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY mux4to1 IS
PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
f : OUT STD_LOGIC ) ;
END mux4to1 ;

ARCHITECTURE dataflow OF mux4to1 IS

BEGIN
WITH s SELECT
f <= w0 WHEN "00",
w1 WHEN "01",
w2 WHEN "10",
w3 WHEN OTHERS ;
END dataflow ;

79 System Design Using FPGA

 VHDL code for a 2-to-4 Decoder
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY dec2to4 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END dec2to4 ;

ARCHITECTURE dataflow OF dec2to4 IS

SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGIN
Enw <= En & w ;
WITH Enw SELECT
y <= “0001" WHEN "100",
"0010" WHEN "101",
"0100" WHEN "110",
“1000" WHEN "111",
"0000" WHEN OTHERS ;
END dataflow ;
80 System Design Using FPGA
 Describing
Combinational Logic
Using
Dataflow Design Style

81 System Design Using FPGA

 MLU Example

82 System Design Using FPGA

 MLU Block Diagram
MUX_0
0 A1
A
1 MUX_4_1
IN0 Y1
MUX_1
NEG_A IN1 0
MUX_2 IN2 OUTPUT Y
1
IN3 SEL0
SEL1

NEG_Y
0 B1
B
1 L1 L0

MUX_3
NEG_B

83 System Design Using FPGA

 MLU: Entity Declaration
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY mlu IS
PORT(
NEG_A : IN STD_LOGIC;
NEG_B : IN STD_LOGIC;
NEG_Y : IN STD_LOGIC;
A: IN STD_LOGIC;
B: IN STD_LOGIC;
L1 : IN STD_LOGIC;
L0 : IN STD_LOGIC;
Y: OUT STD_LOGIC
);
END mlu;

84 System Design Using FPGA

 MLU: Architecture Declarative Section
ARCHITECTURE mlu_dataflow OF mlu IS

SIGNAL A1 : STD_LOGIC;
SIGNAL B1 : STD_LOGIC;
SIGNAL Y1 : STD_LOGIC;
SIGNAL MUX_0 : STD_LOGIC;
SIGNAL MUX_1 : STD_LOGIC;
SIGNAL MUX_2 : STD_LOGIC;
SIGNAL MUX_3 : STD_LOGIC;
SIGNAL L: STD_LOGIC_VECTOR(1 DOWNTO 0);

85 System Design Using FPGA

 MLU - Architecture Body
BEGIN
A1<= NOT A WHEN (NEG_A='1') ELSE
A;
B1<= NOT B WHEN (NEG_B='1') ELSE
B;
Y <= NOT Y1 WHEN (NEG_Y='1') ELSE
Y1;

MUX_0 <= A1 AND B1;

MUX_1 <= A1 OR B1;
MUX_2 <= A1 XOR B1;
MUX_3 <= A1 XNOR B1;

L <= L1 & L0;

with (L) select

Y1 <= MUX_0 WHEN "00",
MUX_1 WHEN "01",
MUX_2 WHEN "10",
MUX_3 WHEN OTHERS;

END mlu_dataflow;
86 System Design Using FPGA
 Behavioral Design Style:
Registers & Counters

87 System Design Using FPGA

VHDL Design Styles
VHDL Design
Styles

dataflow structural behavioral

Concurrent Components and Sequential statements

statements interconnects • Registers
• Shift registers
• Counters
synthesizable • State machines

and more
System Design Using FPGA
if you are careful
88
 Processes in VHDL
• Processes Describe Sequential Behavior
• Processes in VHDL Are Very Powerful
Statements
• Allow to define an arbitrary behavior that may be
difficult to represent by a real circuit
• Not every process can be synthesized
• Use Processes with Caution in the Code to Be
Synthesized
• Use Processes Freely in Testbenches
89 System Design Using FPGA
 Anatomy of a Process

OPTIONAL

[label:] PROCESS [(sensitivity list)]

[declaration part]
BEGIN
statement part
END PROCESS [label];

90 System Design Using FPGA

 Component Equivalent of a Process
clk y
w
priority: PROCESS (clk) a priorit
z
BEGIN b y
IF w(3) = '1' THEN c
y <= "11" ; • All signals which appear on the left
ELSIF w(2) = '1' THEN of signal assignment statement (<=)
y <= "10" ; are outputs e.g. y, z
ELSIF w(1) = c THEN • All signals which appear on the
y <= a and b; right of signal assignment statement
ELSE (<=) or in logic expressions are
z <= "00" ; inputs e.g. w, a, b, c
END IF ;
• All signals which appear in the
END PROCESS ;
sensitivity list are inputs e.g. clk
• Note that not all inputs need to be
included in the sensitivity list

91 System Design Using FPGA

 Registers

92 System Design Using FPGA

 D flip-flop
Graphical symbol Truth table
Clk D Q(t+1)
D Q
 0 0
Clock  1 1
0 – Q(t)
1 – Q(t)
Timing diagram
t1 t2 t3 t4

Clock
D
Q
Time

93 System Design Using FPGA

 D latch
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
D Q
ENTITY latch IS
PORT ( D, Clock : IN STD_LOGIC ; Clock
Q : OUT STD_LOGIC) ;
END latch ;

ARCHITECTURE behavioral OF latch IS

BEGIN
PROCESS ( D, Clock )
BEGIN
IF Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END behavioral;

94 System Design Using FPGA

 D flip-flop
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY flipflop IS D Q
PORT ( D, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ; Clock
END flipflop ;

ARCHITECTURE behavioral OF flipflop IS

BEGIN
PROCESS ( Clock )
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END behavioral ;

95 System Design Using FPGA

 A word on generics
• Generics are typically integer values
• In this class, the entity inputs and outputs should be std_logic
or std_logic_vector
• But the generics can be integer
• Generics are given a default value
• GENERIC ( N : INTEGER := 16 ) ;
• This value can be overwritten when entity is instantiated as a
component
• Generics are very useful when instantiating an often-used
component
• Need a 32-bit register in one place, and 16-bit register in
another
• Can use the same generic code, just configure them
differently
96 System Design Using FPGA
 Counters

97 System Design Using FPGA

 2-bit up-counter with synchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY upcount IS
PORT ( Clear, Clock: IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ) ;
END upcount ;

ARCHITECTURE behavioral OF upcount IS

SIGNAL Count : std_logic_vector(1 DOWNTO 0);
BEGIN 2
upcount: PROCESS ( Clock ) Clear
Q
BEGIN
IF rising_edge(Clock) THEN
IF Clear = '1' THEN
upcount
Count <= "00" ;
ELSE Clock
Count <= Count + 1 ;
END IF ;
END IF;
END PROCESS;
Q <= Count;
END behavioral;
98 System Design Using FPGA
ECE 448 – FPGA and ASIC Design with VHDL
 Shift register

Q(3) Q(2) Q(1) Q(0)

Sin
D Q D Q D Q D Q

Clock

Enable

99 System Design Using FPGA

 Shift Register With Parallel Load
Load

D(3)
D(2) D(1) D(0)
Sin

D Q D Q D Q D Q

Clock

Enable

Q(3) Q(2) Q(1) Q(0)

100 System Design Using FPGA
4-bit shift register with parallel load (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY shift4 IS
PORT ( D: IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
Enable : IN STD_LOGIC ;
Load : IN STD_LOGIC ;
Sin : IN STD_LOGIC ;
Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END shift4 ;

4 Enable 4
D Q
Load
Sin
shift4
Clock
101 System Design Using FPGA
4-bit shift register with parallel load (2)
ARCHITECTURE behavioral OF shift4 IS
SIGNAL Qt : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS (Clock)
BEGIN
IF rising_edge(Clock) THEN
IF Load = '1' THEN
Qt <= D ;
ELSIF Enable = ‘1’ THEN
Qt(0) <= Qt(1) ;
Qt(1) <= Qt(2);
Qt(2) <= Qt(3) ; 4 Enable 4
Qt(3) <= Sin; D Q
END IF ; Load
END IF ; Sin
END PROCESS ; shift4
Q <= Qt; Clock
END behavioral ;
102 System Design Using FPGA
 Finite State Machines
in VHDL

103 System Design Using FPGA

 FSMs in VHDL
• Finite State Machines Can Be Easily Described
With Processes
• Synthesis Tools Understand FSM Description if
Certain Rules Are Followed
• State transitions should be described in a process
sensitive to clock and asynchronous reset signals
only
• Output function described using rules for
combinational logic, i.e. as concurrent statements or
a process with all inputs in the sensitivity list
104 System Design Using FPGA
 Moore FSM
process(clock, reset)

Inputs Next State

function
Next State

clock Present State Present State

reset Register

concurrent Output Outputs

statements function
105 System Design Using FPGA
 Mealy FSM
process(clock, reset)
Inputs Next State
function
Next State Present State
clock Present State
reset Register

Output Outputs
concurrent function

106
statements
System Design Using FPGA
 Moore FSM - Example 1
• Moore FSM that Recognizes Sequence “10”

0 1
0
1
S0 / 0 S1 / 0 1 S2 / 1

reset
0

107 System Design Using FPGA

 Moore FSM in VHDL (1)
TYPE state IS (S0, S1, S2);
SIGNAL Moore_state: state;

U_Moore: PROCESS (clock, reset)

BEGIN
IF(reset = ‘1’) THEN
Moore_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THEN
CASE Moore_state IS
WHEN S0 =>
IF input = ‘1’ THEN
Moore_state <= S1;
ELSE
Moore_state <= S0;
END IF;

108 System Design Using FPGA

 Moore FSM in VHDL (2)
WHEN S1 =>
IF input = ‘0’ THEN
Moore_state <= S2;
ELSE
Moore_state <= S1;
END IF;
WHEN S2 =>
IF input = ‘0’ THEN
Moore_state <= S0;
ELSE
Moore_state <= S1;
END IF;
END CASE;
END IF;
END PROCESS;

Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;

109 System Design Using FPGA

 Mealy FSM - Example 1

• Mealy FSM that Recognizes Sequence “10”

0/0 1/0 1/0

S0 S1

reset 0/1

110 System Design Using FPGA

 Mealy FSM in VHDL (1)
TYPE state IS (S0, S1);
SIGNAL Mealy_state: state;

U_Mealy: PROCESS(clock, reset)

BEGIN
IF(reset = ‘1’) THEN
Mealy_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THEN
CASE Mealy_state IS
WHEN S0 =>
IF input = ‘1’ THEN
Mealy_state <= S1;
ELSE
Mealy_state <= S0;
END IF;
111 System Design Using FPGA
 Mealy FSM in VHDL (2)
WHEN S1 =>
IF input = ‘0’ THEN
Mealy_state <= S0;
ELSE
Mealy_state <= S1;
END IF;
END CASE;
END IF;
END PROCESS;

Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;

112 System Design Using FPGA

Current Technologies
Microcontroller-based systems
DSP processor-based systems
ASIC technology
FPGA technology

System Design Using FPGA 113

Embedded Systems
Examples:
 Communication devices
 Wired and wireless routers and switches
 Automotive applications
 Braking systems, traction control, airbag release systems, and
cruise-control applications
 Aerospace applications
 Flight-control systems, engine controllers, auto-pilots and
passenger in-flight entertainment systems
 Defense systems
 Radar systems, fighter aircraft flight-control systems, radio
systems, and missile guidance systems

System Design Using FPGA 114

Embedded Design in an FPGA
Embedded design in an FPGA consists of the
following:
 FPGA hardware design
 C drivers for hardware
 Software design

System Design Using FPGA 115

Embedded CPUs
 PowerPC 405 (hard core)
 32 bit embedded PowerPC RISC architecture
 Up to 450 MHz
 2x16 kB instruction and data caches
 Memory management unit (MMU)
 Hardware multiply and divide
 Coprocessor interface (APU)
 Embedded in Virtex-II Pro and Virtex-4
 PLB and OCM bus interfaces

 MicroBlaze (soft core)

 32 bit RISC architecture
 2 64 kB instruction and data caches
 Barrel Shifter
 Hardware multiply and divide
 OPB and LMB bus interfaces
Images by Xilinx

 Others
 NIOS (Altera), ARM, PicoBlaze [soft core; 8-bit] (Xilinx), ...

System Design Using FPGA 116

 Processor in FPGA
 Softcore microprocessor: using FPGA resources only
 Synthesize and compiling need: tools are very important
 Xilinx offering: MicroBlaze & PicoBlaze
 Altera offering: NIOS

 Hardcore microprocessor: hardwired in FPGA architecture

 3rd party tools
 Xilinx: (Virtex II Pro) PowerPC from IBM
 Altera: (Excalibur APEX) ARM922T from ARM

System Design Using FPGA 117

 Embedded Processors
 Hard core  Soft core
 Faster  Slower
 Fixed position  Can be placed anywhere
 Few devices  Applicable to many devices

 Virtex-4 Processors:

Embedded Core Max Clock Block

Slices PLBs
Processor Type Frequency RAMs
PowerPC Hard 222 MHz 1000 250 9
MicroBlaze
PowerPC
MicroBlaze
PicoBlaze
Microblaze Soft 180 MHz 940 235 9
Picoblaze Soft 221 MHz 333 84 3
Picoblaze
Soft 233 MHz 274 69 3
(optimized)

System Design Using FPGA 118

MicroBlaze-based Embedded Design

I-Cache

BRAM Local Memory MicroBlaze

BRAM Flexible Soft IP
Configurable
Bus 32-Bit RISC Core Sizes
D-Cache Possible in Dedicated Hard IP
BRAM Virtex-II Pro PowerPC
405 Core
Instruction Data
LocalLink™ OPB
Arbiter
FIFO Channels PLB

Arbiter
Bus
On-Chip Peripheral Bus Bridge
Processor Local Bus
0,1…….32
e.g.
Hi-Speed Memory GB
Custom Custom Peripheral Controller E-Net

Functions Functions
10/100 On-Chip
UART
E-Net Peripheral

Off-Chip FLASH/SRAM
Memory
Source: Xilinx
System Design Using FPGA 119
Microblaze
 32-bit soft processor solution
 soft core, meaning that it is implemented
using general logic primitives rather than a
hard, dedicated block in the FPGA
 MicroBlaze soft core licensed as part of the
Xilinx Embedded Development Kit (EDK)
 Complete embedded development solution
that includes:
 A library of peripheral IP cores,
 The award-winning Xilinx Platform Studio tool suite
for intuitive hardware system creation
 A Built-On Eclipse software development
environment
 GNU compiler, debugger and more.
 The MicroBlaze processor is also supported
by third party development tools and Real
Time Operating Systems (RTOS)

System Design Using FPGA 120

 PicoBlaze KCPSM3 processor
 Author: Ken Chapman, Xilinx; [email protected]
 VHDL Core with assembler: free from www.xilinx.com
 Main parameters:
 8 bit CPU, 1 BRAM 1024x18 for program, only 96 slices (5% of
xc3s200)
 16 registers, Scratch pad memory 64 byte, 8bit I/O bus, 8bit port
address
 all instructions take constantly 2 clock cycles, 1 level of interrupt
 KCPSM3 includes Assembler, RS232 macros and uart_clock demo.
 Optimized for Virtex E, Virtex 2, and Spartan 3
 Our design is reusing parts of Ken’s uart_clock demo
 We add inter-processor connect, VGA support and Floating point
HW
 We add hazard free access to DP BRAM from Master and Worker
PicoBlaze

System Design Using FPGA 121

 Outline

 Introduction to ASIC design: What is FPGA?

 Xilinx FPGA
 Xilinx ISE Design flow
Embedded System Design: Hard-processor PowerPC and
Soft-processors MicroBlaze and PicoBlaze
 Xilinx Platform Studio Design Flow using MicroBlaze
 Xilinx ISE Embedded System Design flow using PicoBlaze

System Design Using FPGA 122

Traditional Embedded System

Power Supply
Ethernet Audio CLK
CLK
MAC Codec

GP I/O Interrupt
Controller
Timer
Address
Decode
Unit
CPU UART
L
(uP / DSP) Co- C
Memory Proc. custom
CLK Controller IF-logic

SRAM SRAM SRAM Display

SDRAM SDRAM Controller

System Design Using FPGA 123

Configurable System on a Chip (CSoC)

Audio
Codec EPROM

Power Supply

L
C

SRAM SRAM SRAM SDRAM SDRAM

System Design Using FPGA 124

Reconfigurable System on a Chip (SoC)

How to build such a system ?

1. Overview:
 Xilinx EDK / MicroBlaze Soft CPU core
 Design- / Tool-Flow

2. Demonstration:
 Create a simple system
 Implement the system on a Xilinx Spartan-III FPGA

System Design Using FPGA 125

Soft CPU Core: MicroBlaze (Xilinx Inc.)

System Design Using FPGA 126

 MicroBlaze: Architecture & Features
Architecture

OPB

LMB

Features • RISC
• Thirty-two 32-bit general purpose registers
• 32-bit instruction word with three operands and two addressing modes
• Separate 32-bit instruction and data buses OPB (On-chip Peripheral Bus)
• Separate 32-bit instruction and data buses LMB (Local Memory Bus)
• Hardware multiplier (in Virtex-II and subsequent devices)

System Design Using FPGA 127

 Bus Configuration 3

• Instructions and data from internal BRAMs (fast)

• Data from external memory

System Design Using FPGA 128

Embedded Development
Tool Flow Overview
Standard Embedded SW Standard FPGA HW
Development Flow Development Flow
C Code VHDL/Verilog

Compiler/Linker Synthesizer
(Simulator) Simulator

Object Code Place & Route

? ?
CPU code in CPU code in
off-chip on-chip
memory memory Download to FPGA

Download to Board & FPGA

Debugger

Source: Xilinx
System Design Using FPGA 129
EDK
 The Embedded Development Kit (EDK) consists of the
following:
 Xilinx Platform Studio – XPS
 Base System Builder – BSB
 Create and Import Peripheral Wizard
 Hardware generation tool – PlatGen
 Library generation tool – LibGen
 Simulation generation tool – SimGen
 GNU software development tools
 System verification tool – XMD
 Virtual Platform generation tool - VPgen
 Software Development Kit (Eclipse)
 Processor IP
 Drivers for IP
 Documentation
 Use the GUI or the shell command tool to run EDK

System Design Using FPGA 130

 Demonstration:
An application using PicoBlaze: [Using Xilinx ISE tool]

System Design Using FPGA 131

Demonstration…

System Design Using FPGA 132

That’s all about FPGA-based(Xilinx)
Embedded System Design

System Design Using FPGA 133

For more information...
Xilinx EDK & MicroBlaze: www.xilinx.com/edk
Embedded Processing:

http://www.xilinx.com/products/design_resources/proc_central/index.htm

Xilinx Platform Studio user guide: http://www.xilinx.com/ise/embedded/ps_ug.pdf

MicroBlaze user guide: http://www.xilinx.com/bvdocs/userguides/ug133.pdf

PicoBlaze user guide:

http://www.xilinx.com/bvdocs/userguides/ug129.pdf

http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm

http://www.xilinx.com/ipcenter/processor_central/picoblaze/picoblaze_user_resources.
htm

Spartan Kit Data sheet: http://www.xilinx.com/bvdocs/publications/ds099.pdf

System Design Using FPGA 134

Questions?

System Design Using FPGA 135