EEE/CSE 226

Assembly Language Programming & Microprocessors

(Intel)

• What the course is about

– Assembly language programming

– Computer interfacing

– Introduction to architecture and instruction set ideas

– Computer system design

– How things work

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SDK-86
• The SDK-86 single board computer originally was a kit.
Intel sold the rights to it to URDA, and it is still available as
an assembled board.

<-- Serial port

<-- 7 segment displays

<--- Keypad
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EV80C186EB

• Ev80C186 Evaluation Board

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80C186EB

• 80C186EB Interfaces as seen in Intel ApBUILDER

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80C186EB

• 80C186EB Block Diagram

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80C186EB

• 80C186EB evaluation board block diagram

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226 Lab Software

\C:

\DOS

EDIT text editor

\WINDOWS

NOTEPAD text editor

POWERPOINT VIEWER

APBUILDER

80C186EB MANUAL

80C186EB DATA SHEET

\226LAB

ASM86.EXE

LINK86.EXE

LOC86.EXE
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8086 Features

• 16-bit Arithmetic Logic Unit

• 16-bit data bus (8088 has 8-bit data bus)

• 20-bit address bus - 220 = 1,048,576 = 1 meg

The address refers to a byte in memory. In the 8088, these bytes come in on
the 8-bit data bus. In the 8086, bytes at even addresses come in on the low
half of the data bus (bits 0-7) and bytes at odd addresses come in on the upper
half of the data bus (bits 8-15).

The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations. The 8088 needs two operations in either case.

The least significant byte of a word on an 8086 family microprocessor is at the

lower address.

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8086 Architecture

• The 8086 has two parts, the Bus Interface Unit (BIU) and the
Execution Unit (EU).

• The BIU fetches instructions, reads and writes data, and computes the
20-bit address.

• The EU decodes and executes the instructions using the 16-bit ALU.

• The BIU contains the following registers:

IP - the Instruction Pointer

CS - the Code Segment Register
DS - the Data Segment Register
SS - the Stack Segment Register
ES - the Extra Segment Register

The BIU fetches instructions using the CS and IP, written CS:IP, to contruct
the 20-bit address. Data is fetched using a segment register (usually the DS)
and an effective address (EA) computed by the EU depending on the
addressing mode.

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8086 Block Diagram

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8086 Architecture
The EU contains the following 16-bit registers:

AX - the Accumulator
BX - the Base Register
CX - the Count Register
DX - the Data Register
SP - the Stack Pointer \ defaults to stack segment
BP - the Base Pointer /
SI - the Source Index Register
DI - the Destination Register

These are referred to as general-purpose registers, although, as seen by

their names, they often have a special-pupose use for some instructions.

The AX, BX, CX, and DX registers can be considers as two 8-bit registers, a
High byte and a Low byte. This allows byte operations and compatibility with
the previous generation of 8-bit processors, the 8080 and 8085. 8085 source
code could be translated in 8086 code and assembled. The 8-bit registers are:

AX --> AH,AL
BX --> BH,BL
CX --> CH,CL
DX --> DH,DL
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8086 Architecture

The EU also contains the Flag Register which is a collection of condition

bits and control bits. The condition bits are set or cleared by the execution
of an instruction. The control bits are set by instructions to control some
operation of the CPU.

Bit 0 - CF Carry Flag - Set by carry out of msb

Bit 2 - PF Parity Flag - Set if result has even parity
Bit 4 - AF Auxiliary Flag - for BCD arithmetic
Bit 6 - ZF Zero Flag - Set if result is zero
Bit 7 - SF Sign Flag = msb of result
Bit 8 - TF Single Step Trap Flag
Bit 9 - IF Interrupt Enable Flag
Bit 10 - DF String Instruction Direction Flag
Bit 11 - OF Overflow Flag

Bits 1, 3, 5, 12-15 are undefined.

Bits 0-7 are 8085 compatible.

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8086 Programmer’s Model

ES Extra Segment
BIU registers CS Code Segment
(20 bit adder) SS Stack Segment
DS Data Segment
IP Instruction Pointer

AX AH AL Accumulator
BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
EU registers
DI Destination Index Register
16 bit arithmetic
FLAGS

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Segments
Address
0H
Segment Starting address is segment

register value shifted 4 places to the left.

CODE
64K Data
STACK Segment

DATA

EXTRA  CS:0
64K Code
Segment
Segment
Registers

Segments are < or = 64K,

can overlap, start at an address
that ends in 0H. 0FFFFFH
MEMORY
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8086 Memory Terminology

Memory Segments
Segment 0H
Registers
01000H
DS: 0100H DATA
10FFFH

0B2000H
SS: 0B200H STACK
0C1FFFH

ES: 0CF00H 0CF000H

EXTRA
0DEFFFH

CS: 0FF00H
0FF000H
CODE
0FFFFFH

Segments are < or = 64K and can overlap.

Note that the Code segment is < 64K since 0FFFFFH is the highest address.
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The Code
Segment
0H

4000H
CS: 0400H

IP 0056H 4056H
CS:IP = 400:56
Logical Address

Memory
0400 0
Segment Register

Offset + 0056
Physical or 04056H 0FFFFFH
Absolute Address

The offset is the distance in bytes from the start of the segment.
The offset is given by the IP for the Code Segment.
Instructions are always fetched with using the CS register.

The physical address is also called the absolute address.

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The Stack Segment
0H

0A00 0A000H
SS:

0A100H
SP 0100 SS:SP

Memory
0A00 0
Segment Register

Offset + 0100

Physical Address 0A100H 0FFFFFH

The offset is given by the SP register.

The stack is always referenced with respect to the stack segment register.
The stack grows toward decreasing memory locations.
The SP points to the last or top item on the stack.

PUSH - pre-decrement the SP

POP - post-increment the SP

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The Data Segment
0H

05C00H
DS: 05C0

05C50H
EA 0050 DS:EA

Memory
05C0 0
Segment Register

Offset + 0050

Physical Address 05C50H 0FFFFFH

Data is usually fetched with respect to the DS register.

The effective address (EA) is the offset.
The EA depends on the addressing mode.

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Addressing
Modes
Assembler directive
SAM DW 25H SAM is defined as a word (16-bit) variable, i.e., a
memory location that contains 25H.

FRED EQU 20H FRED is not a memory location but a constant.

Direct Addressing

MOV AX,SAM [SAM]  AX, the contents of SAM is put into AX.
The cpu goes to memory to get data.
25H is put in AX.
Immediate Addressing

MOV AX,FRED FRED = 20H  AX, 20H is put in AX.

Does not go to memory to get data.
Data is in the instruction.

MOV AX, OFFSET SAM The offset of SAM is just a number.

The assembler knows which mode to encode by the way the

operands SAM and FRED are defined.

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Addressing
Modes
Memory MOV AX,SAM
0H
[200ABH] = 25H

DS [200ACH] = 00H

Direct Addressing
SAM
Data is at DS:SAM
25H

0FFFFFH

Shift segment one digit

Example to the left and add offset
DS = 2000H 2000 0H
Offset SAM = 0ABH ABH
200ABH
DS:SAM = 2000H:0ABH Logical Address
= 200ABH Absolute or Physical Address

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Addressing
Modes

Register Addressing MOV AX,BX AX BX

Register Indirect Addressing MOV AX,[BX] AX DS:BX

Can use BX or BP -- Based Addressing (BP defaults to SS)

or DI or SI -- Indexed Addressing
The offset or effective address (EA) is in the base or index register.

Register Indirect with Displacement MOV AX,SAM[BX]

Indexed with displacement AX DS:BX + Offset SAM
Based with displacement
AX DS:EA
where EA = BX + offset SAM

Based-Indexed Addressing MOV AX,[BX][SI] EA = BX + SI

Based-Indexed w/Displacement MOV AX,SAM[BX][DI]

EA = BX + DI + offset SAM

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Addressing
Modes

Instructions are always fetched from the Code Segment. The IP

points at the next instruction to be executed at CS:IP.

Data usually comes from the data segment. However, data can
be fetched from any segment by use of the segment override prefix.

MOV AX,ES:[BX] data at ES:BX

MOV AX,[BP] data at SS:BP
MOV AX,CS:[SI] data at CS:SI
MOV AX,[BX] data at DS:BX

MOV AX,SAM[BP] is encoded as MOV AX,DS:SAM[BP], i.e., the

assembler generates a segment override to the segment where
SAM is defined (DS assumed in this example).

MOV destination, source

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Addressing
Modes

Branch Related Instructions

JUMPS and CALLS

NEAR
Intrasegment Direct -- IP relative displacement
(CS does not change) new IP = old IP + displacement
Allows program relocation with
no change in code.
Indirect -- new IP is in memory or a register.
All addressing modes apply.

FAR
Intersegment Direct -- new CS and IP are encoded in
(CS changes) the instruction.

Indirect -- new CS and IP are in memory.

All addressing modes apply
except immediate and register.

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Assembly Language

The Assembler is a program that reads the source program as data and
translates the instructions into binary machine code. The assembler
outputs a listing of the addresses and machine code along with the
source code and a binary file (object file) with the machine code.

Most assemblers scan the source code twice -- called a two-pass assembler.
• The first pass determines the locations of the labels or identifiers.
• The second pass generates the code.

To locate the labels, the assembler has a location counter. This counts the
number of bytes required by each instruction.
• When the program starts a segment, the location counter is zero.
• If a previous segment is re-entered, the counter resumes the count.
• The location counter can be set to any offset by the ORG directive.

In the first pass, the assembler uses the location counter to construct a
symbol table which contains the offsets or values of the various labels.
The offsets are used in the second pass to generate operand addresses.

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Assembly Language

In addition to the offset of the variable, the symbol table also contains
the type of variable, e.g.,

Constant FIVE EQU 5

Byte NUM1 DB 17H

Word WORDNUM DW 2450

Near Label START: MOV ...

etc.

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Pseudo
Code
Programming with no rules of syntax.

Can use structured constructs.

Example

PROGRAM Multiply by repeated addition.

Initialize product to zero. (product in AX)

Load two numbers to multiply. (Put count in CX)
Begin
Do while CX > 0
replace AX by AX + DX
decrement CX
End Do
End

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Functional Level Flow
Chart AX = A
START A = BC
DX = B
CX = C
A 0
B Multiplicand
C Count

A A+B

C C-1

NO
C=0?

YES

END

Multiplication by Repeated Addition.

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Source
File
NAME MULBYADD
;
;This program does multiplication by repeated addition
;
ASSUME CS:SEG0,DS:SEG0,SS:SEG0,ES:SEG0 ; Segments
overlap.
SEG0 SEGMENT AT 10H ; Segment registers assumed to be 10H.
ORG 100H ; Program origin within the segment.
START: MOV AX,SEG0 ; Load segment value.
MOV DS,AX ; Set up data segment.
MOV AX,0 ; Initialize the product.
MOV DX,6 ; Number to be added.
MOV CX,7 ; Loop count or number of repeats.
MLOOP: ADD AX,DX
DEC CX
JNZ MLOOP
INT 3 ; Return to monitor
SEG0 ENDS
END START

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List
File

LOC OBJ LINE SOURCE

1 NAME MULBYADD
2 ;
3 ;This program does multiplication by repeated addition
4 ;
5 ASSUME CS:SEG0,DS:SEG0,SS:SEG0,ES:SEG0 ; Segments overlap.
---- 6 SEG0 SEGMENT AT 10H ; Segment registers assumed to be 10H.
0100 7 ORG 100H ; Program origin within the segment.
0100 B81000 8 START: MOV AX,SEG0 ; Load segment value.
0103 8ED8 9 MOV DS,AX ; Set up data segment.
0105 B80000 10 MOV AX,0 ; Initialize the product.
0108 BA0600 11 MOV DX,6 ; Number to be added.
010B B90700 12 MOV CX,7 ; Loop count or number of repeats.
010E 03C2 13 MLOOP: ADD AX,DX
0110 49 14 DEC CX
0111 75FB 15 JNZ MLOOP
0113 CC 16 INT 3 ; Return to monitor
---- 17 SEG0 ENDS
18 END START

ASSEMBLY COMPLETE, NO ERRORS FOUND

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More Assembler Directives

ASSUME Tells the assembler what segments to use.

SEGMENT Defines the segment name and specifies that the

code that follows is in that segment.

ENDS End of segment

ORG Originate or Origin: sets the location counter.

END End of source code.

NAME Give source module a name.

DW Define word

DB Define byte.

EQU Equate or equivalence

LABEL Assign current location count to a symbol.

$ Current location count

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Assembly Example

Location # Bytes NAME EXAMPLE

Counter ASSUME CS:CSEG,DS:DSEG
DSEG SEGMENT ;Start data segment
0 10H ORG 10H ; move down 10H byt
10H 2 COUNT DW 345 ;define a word
12H 100H ARRAY DB 100H DUP(?) ;declare uninitialized
112H ... DSEG ENDS ; array
...
0 0 CSEG SEGMENT
0 3 START: MOV AX,DSEG
3 2 MOV DS,AX
5 4 MOV CX,COUNT
9 1 REPEAT:DEC CX
A .
.
.
CSEG ENDS

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Symbol
Table
Symbol Offset Segment Type

DSEG 0 Segment
COUNT 10H DSEG Word variable
ARRAY 12H DSEG Byte variable
.
.
.
CSEG 0 Segment
START 0 CSEG Near label
REPEAT 9H CSEG Near label
.
.
.
The program source should be organized in the following order.

Data segments
Stack
Code
Procedures (subroutines)
Main routine

Therefore, labels and variables are defined before they are used
by the code, except for forward jumps.
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Debuggin
g
When developing a program,write and test small sections or modules. You can develop you own
library of tested routines.

Check that you have not accidentally reversed source and destination operands.

Assuming that you have assembled, linked, located, and downloaded your program without any
errors, what do you do when your program
does not work. You use a debugger and two standard techniques, single stepping and breakpoints.

You should know what is the result of executing each instruction. In single stepping through a
program, you execute one instruction at a time and review the registers and contents any relevant
memory location after each step. This is like watching a slow motion replay of your program
execution.
Obviously you cannot single step through a long program every time you need to debug it. You can
set a breakpoint so that the program can run through code that has previously been checked and
stop at the point in the program where the problem is. This allows you to run through procedures
that have been debugged. You can run through a number of instructions before stopping to
examine registers and memory.
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Instruction
Encoding
Machine code (the encoded instruction) specifies things such as
1. The operation to be performed.
2. The operand or operands to use.
3. Byte or word operations.
4. Whether data is in a register or memory.
5. If data is in memory, how the address is generated.

In the 8086, the machine-code instructions can vary from one to six bytes
with additional bytes for prefixes such as segment override.

Single-Byte Instructions
1. No operand, e.g., the clear carry instruction CLC has the code 0F8H.

2. Single operand, e..g., INCrement 16-bit register.

The instruction format is [opcode | reg] = [01000 reg].
The register encoding is: AX 000
CX 001
DX 010
BX 011
SP 100
BP 101
SI 110
DI 111
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Instruction
Encoding
A more general 2,3, or 4-byte form allows bytes or word in registers and
memory to be operated on. This form has a split opcode.

[opcode | w] [mod | opcode | r/m]

w=0 byte mod 11 r/m is register field.

10 16-bit displacement, hi:low.
01 8-bit displacement, sign extended to 16.
00 16-bit displacement, if r/m = 110.

For 8-bit registers, the code is AL 000 r/m BX + SI + DISP

CL 001 BX + DI + DISP
DL 010 BP + SI + DISP
BL 011 BP + DI + DISP
AH 100 SI + DISP
CH 101 DI + DISP
DH 110 BP + DISP (unless mod 00)
BH 111 BX + DISP

Example
[1111111 0] [11 000 001] INC CL
INC byte reg INC CL

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Instruction
Encoding

op w mod op r/m disp

[ 1111111 1 ] [ 01 000 100 ] [01011100 ] = FF44 5C

This is the instruction INC SAM[SI] where

opcode 1111111x xx 000 xxx is INC

w = 1 means the operand is a word.
mod = 01 means 8-bit displacement sign extended to 16 bits.
r/m = 100 means add displacement to SI.
offset of SAM = 5CH

IF SI = A086, the offset into the data segment of the word in

memory to increment is

A086
+005C
A0E2 = EA

The contents of the word at DS:A0E2 is incremented.

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Examples of 8086 Instruction Formats

opcode One byte instruction - implied operand(s)

opcode reg One byte instruction - register mode.

opcode 11 reg r/m Register to register

dw

Opcode dw
00 reg r/m Register Indirect

Register to/from memory with 8 or 16 bit displacement

Opcode d w mod reg r/m disp LOW disp HIGH

Immediate operand to register

opcode 11 opcode r/m data LOW data HIGH

Immediate operand to memory with 16-bit displacement

opcode mod opcode r/m disp LOW disp HIGH

data LOW data HIGH

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Special Case - Direct Addressing

Assume SAM is a word variable with offset 1234H.

How do we encode ADD AX,SAM?

The format for the ADD registers and memory instruction is

[ 0 0 0 0 0 0 d w] [ mod reg r/m] [ disp LO ] [ disp HI]

reg is source if d = 0 and destination if d = 1.

Bytes are added if w = 0 and word are added if w = 1.

Direct addressing is the special case where mod = 00 and r/m = 110.

Therefore the machine code is

[ 0 0 0 0 0 0 1 1 ] [0 0 0 0 0 1 1 0] [0 0 1 1 0 1 0 0] [0 0 0 1 0 0 1 0 ] = 03 06 34 12
AX is AX 3 4 1 2
destination
Word operation
Due to the special case, the instruction ADD AX,[BP] is encoded as
ADD AX,Disp[BP] where Disp = 0.

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Loops and Conditional
Jumps
All loops and conditional jumps are SHORT jumps, i.e., the target must
be in the range of an 8-bit signed displacement (-128 to +127).

The displacement is the number that, when added to the IP, changes the
IP to point at the jump target. Remember the IP is pointing at the next
instruction when this occurs.

The loop instructions perform several operations at one time but do not
change any flags.

LOOP decrements CX and jumps if CX is not zero.

LOOPNZ or LOOPNE -- loop while not zero or not equal: decrements CX
and jumps if CX is not zero or the zero flag ZF = 0.
LOOPZ or LOOPE -- loop while zero or equal: decrements CX and jumps
if CX is zero or the zero flag ZF = 1.

The conditional jump instructions often follow a compare CMP or TEST

instruction. These two instructions only affect the FLAG register and not
the destination. CMP does a SUBtract (dest - src) and TEST does an AND.

For example, if a CMP is followed by a JG (jump greater than), then the

jump is taken if the destination is greater than the source.
Test is used to see if a bit or bits are set in a word or byte such as when
determining the status of a peripheral device.
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Conditional
Jumps
Name/Alt Meaning Flag setting
JE/JZ Jump equal/zero ZF = 1
JNE/JNZ Jump not equal/zero ZF = 0
JL/JNGE Jump less than/not greater than or = (SF xor OF) = 1
JNL/JGE Jump not less than/greater than or = (SF xor OF) = 0
JG/JNLE Jump greater than/not less than or = ((SF xor OF) or ZF) = 0
JNG/JLE Jump not greater than/ less than or = ((SF xor OF) or ZF) = 1
JB/JNAE Jump below/not above or equal CF = 1
JNB/JAE Jump not below/above or equal CF = 0
JA/JNBE Jump above/not below or equal (CF or ZF) = 0
JNA/JBE Jump not above/ below or equal (CF or ZF) = 1

JS Jump on sign (jump negative) SF = 1

JNS Jump on not sign (jump positive) SF = 0
JO Jump on overflow OF = 1
JNO Jump on no overflow OF = 0
JP/JPE Jump parity/parity even PF = 1
JNP/JPO Jump no parity/parity odd PF = 0

JCXZ Jump on CX = 0 ---

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Loops and
Strings name sholoop
dseg segment at 200H
string db 'This is a string.'
endstr equ $ - offset string ; label whose offset is the
dseg ends ; length of the string
sseg segment at 100H
dw 200H dup(?)
stktop label word ; location after stack
sseg ends
extrn outchar:near
cseg segment at 4000H
assume cs:cseg,ds:dseg,ss:sseg
start: mov ax,dseg
mov ds,ax ; set up data segment
mov ax,sseg
mov ss,ax ; set up stack segment
mov sp,offset stktop ; sp is decremented first
mov cx,offset endstr ; length of string
mov bx,offset string ; points at string
back: mov al,[bx] ; get a character
call outchar ; output one character
inc bx ; point at next character
loop back ; cx=cx-1, back if cx not 0
cseg ends
end start
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Procedures

A procedure or subroutine is invoked by the CALL instruction. Calls can be

intrasegment (NEAR) and intersegment (FAR), and direct (address in
instruction) or indirect (address in memory).

The other instruction required with a procedure is the RET or return.

Two assembler directives are used, the PROC and ENDP directives are
used to begin and end the procedure. For example:

proc_1 proc near

...
code for procedure
...
ret
proc_1 endp

A near CALL pushes the IP onto the STACK before changing the IP to start
executing the procedure. The RET restores the IP so the program can
pick up from where it left off, i.e., the instruction right after the CALL.

The far CALL pushes both CS and IP onto the STACK and the RET
restores them to their values before the call (assuming the SP is pointing
at the IP on the stack when the RET is executed).
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Parameter Passing

There are several ways of passing information or parameters to a procedure.

1. Put the parameters in certain registers. This is the modern approach

with RISC architectures that have many registers.

2. Put the parameters named memory locations. Uses memory locations.

3. Use the STACK. This also uses memory, but only temporarily. Since
the 8086 has a limited set of registers, parameter passing on the stack
is widely used, especially with compiled code.

The primary instructions for dealing with the stack are the PUSH and POP
instructions. These instructions only have word operands and manipulate
the stack pointer.

The PUSH instruction first decrements the SP by two before pushing the data,
i.e., SP <---- SP - 2 and push word to SS:SP.

The POP instruction first pops the word to the desired location and then
increments SP by 2, i.e. push the word and then SP <----- SP + 2.

The next example shows how to use the stack in a procedure that computes
c = A - B.
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Stack Example
AMB PROC FAR
A DW xxxx PUSH BP ;Index into stack
B DW xxxx MOV BP,SP ;using BP
C DW ? MOV SI,[BP+10] ; offset of A
... MOV AX,[SI]
MOV AX,offset A MOV SI,[BP+8] ;offset of B
MOV BX,offset B SUB AX,[SI]
MOV CX,offset C MOV SI,[BP+6] ;offset of C
PUSH AX MOV [SI],AX
PUSH BX POP BP
PUSH CX RET 6 ;discard parameters, i.e
CALL AMB AMB ENDP ; add 6 to SP after return.
... low memory
BP <---SP
IP <---SP+2
CS <---SP+4
offset C <---SP+6
offset B <---SP+8
offset A <---SP+10
Stack after first instruction
of AMB has been executed.
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Bus Structure

Address Bus

System Bus Data Bus

Control Bus

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Pinout
s

See Fig 7-2 in

textbook and
Appendix A.

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8086 Pins

The 8086 comes in a 40 pin package which means that some pins have
more than one use or are multiplexed. The packaging technology of time
limited the number of pin that could be used.

In particular, the address lines 0 - 15 are multiplexed with data lines 0-15,
address lines 16-19 are multiplexed with status lines. These pins are

AD0 - AD15, A16/S3 - A19/S6

The 8088 does not have the upper 8 data lines so the pins are A8 - A15.

The 8086 has one other pin that is multiplexed and this is BHE’/S7.
BHE stands for Byte High Enable. This is an active low signal that is
asserted when there is data on the upper half of the data bus. There is no
need for this signal on an 8088.

The 8086 has two modes of operation that changes the function of some pins.
The SDK-86 uses the 8086 in the minimum mode with the MN/MX’ pin tied to
5 volts. This is a simple single processor mode. The IBM PC uses an 8088
in the maximum mode with the MN/MX” pin tied to ground. This is the mode
required for a coprocessor like the 8087.

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8086 Pins

In the minimum mode the following pins are available.

HOLD When this pin is high, another master is requesting control of the
local bus, e.g., a DMA controller.

HLDA HOLD Acknowledge: the 8086 signals that it is going to float

the local bus.

WR’ Write: the processor is performing a write memory or I/O operation.

M/IO’ Memory or I/O operation.

DT/R’ Data Transmit or Receive.

DEN’ Data Enable: data is on the multiplexed address/data pins.

ALE Address Latch Enable: the address is on the address/data pins.

This signal is used to capture the address in latches to establish the
address bus.

INTA’ Interrupt acknowledge: acknowledges external interrupt requests.

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8086 Pins

The following are pins are available in both minimum and maximum modes.

VCC + 5 volt power supply pin.

GND Ground

RD’ READ: the processor is performing a read memory or I/O operation.

READY Acknowledgement from wait-state logic that the data transfer will
be completed.

RESET Stops processor and restarts execution from FFFF:0. Must be high
for 4 clocks. CS = 0FFFFH, IP = DS = SS = ES = Flags = 0000H, no
other registers are affected.

TEST’ The WAIT instruction waits for this pin to go low. Used with 8087.

NMI Non Maskable Interrupt: transition from low to high causes an

interrupt. Used for emergencies such as power failure.

INTR Interrupt request: masked by the IF bit in FLAG register.

CLK Clock: 33% duty cycle, i.e., high 1/3 the time.
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 EEE/CSE 226
Timin
g

Figure 7-1(b) of Textbook

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