KAKINADA INSTITUTE OF TECHNOLOGY AND SCIENCE

[An Institute With Permanently Affiliated by JNTU Kakinada, Approved by AICTE, Accredited By NAAC With
A Grade,2(F),12(B) ISO Certified]

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

UNDER THE GUIDENCE OF

Ms. U. SRAVANA JYOTHI M.Tech

PRESENTED BY
R.BHUSHANA RAO (20JQ1A0437)
K.S.MANEESH (20JQ1A0419)
V.REAVATHI (20JQ1A0442)
K.VEERABABU (20JQ1A0418)
 CONTENTS
1. TITLE OF THE PROJECT
2. ABSTRACT
3. INTRODUCTION
4. EXISTING METHOD
5. PROPOSED METHOD
6. TECHNICAL OVERVIEW
7. BLOCK DIAGRAM
8. TABLE
9. RESULTS
10. COMPARISION OF RESULTS
11. ADVANTAGES
12. APPLICATIONS
13. CONCLUSION
14. FUTURE SCOPE
 TITLE OF THE PROJECT

POWER OPTIMIZATION IN CONFIGURABLE

ALU USING CLOCK GATING TECHNIQUES
 ABSTRACT
Reduction in power dissipation is an essential design issue in VLSI circuit. One of the important blocks in
any processor is the Arithmetic Logic Unit and it performs arithmetic and logical operations. The clock
network is a major source of power dissipation so we can reduce significant amount of power if we can gate
the clock whenever it isn’t required. So low power ALU is designed using clock gating techniques besides
using PIPO registers. By giving specific opcode, we can enable the specific operation and other operations
are in inactive mode, so we can see less power dissipation in ALU. Low power ALU is having two 8-bit
input data with Cin, bin, enable and 2-bit shift data and a decoder 4:16 to select the 16 operations by giving
4-bit opcode to it as an input with start enable function. At each iteration the proposed design is implemented
with one of these clock gating techniques i.e. latch free clock gating technique, latch-based clock gating
technique with parallel in parallel out (PIPO) shift registers. The Whole design is implemented in Xilinx
Vivado 2018.2 tool and the power reports were calculated using Xilinx ISE 14.7 tool.
 INTRODUCTION

Reducing power consumption in VLSI circuits is crucial, especially as technology scales down, increasing
power leakage and dissipation. Modern designs prioritize area, delay, testability, and power. Consumers
demand lightweight, responsive, and heat-efficient devices, such as in mobile phones where integrating
multiple functions can increase power and heat. Scaling down technology for smaller area can also raise
power consumption.
To address these issues and create efficient systems, low-power techniques are vital. Power comprises static
(off-state) and dynamic (during transitions) components. This work primarily focuses on minimizing
dynamic power by reducing signal activities. Clock gating controls active clock periods, reducing power use.
Operation selection ensures only specific functions are active, limiting signal transitions in inactive
operations and lowering dynamic power.
ALU :
The Arithmetic Logic Unit (ALU) is a critical component of a computer's
Central Processing Unit (CPU), responsible for a wide range of arithmetic
and logical operations. It takes input data, known as operands, along with a
control code from the CPU's control unit to perform specific operations,
producing an output result. These operations include arithmetic tasks like
addition, subtraction, and logic operations such as AND, NOT, OR, and
more.
Digital systems can be described at different levels of abstraction, with the
highest level being the behavioral description. Behavioral modeling focuses
on what a system does without delving into its internal components or
connections. In this context, an 8-bit ALU is implemented using behavioral Fig. 1. Basic ALU Structure

modeling in Verilog. This approach uses process statements to describe

system behavior over time. Processes are declared within the architecture and
allow for sequential statements to capture the system's operations.
 EXISTING METHOD

 Existing work presents 8-bit Arithmetic and Logic unit that performs various arithmetic and logical operations.
 Here, arithmetic operations are addition, subtraction, multiplication and division and logical operations are
AND, NAND, OR, NOR, XOR, XNOR, arithmetic left and right shift, logical left and right shift, 1’s
compliment and 2’s compliment.
 For shift operations, we designed to shift the bits up to three bits.
 DISADVANTAGES:
1. HIGH POWER CONSUMPTION: The ALU designed in this method doesn’t have any power reduction
techniques employed, due to this the power consumption is very high.
2. MORE DYNAMIC POWER DISSIPATION: This ALU has the clock which is active all the time even
when it is not required due to this the dynamic power dissipation is high
 PROPOSED METHOD

 In our proposed work, we mainly focused on dynamic power dissipation and it is reduced by making less
signal activities in proposed design.
 The clock network is a major source of power dissipation so we can reduce significant amount of power if we
can gate the clock whenever it isn’t required.
 By using operation selection, we can make active specific operation only and other operations are in inactive
mode then we can’t see signal transitions in other operations so we can get less dynamic power dissipation
when operation selection instruction used.
 Here we are using Latch free clock gating and Latch based clock gating techniques.
 TECHNICAL OVERVIEW

1. LATCH FREE CLOCK GATING

TECHNIQUE:
 In this technique, single two input basic gate is used as
AND for clock gating technique.

 The main Drawback of this technique is that if enable

signal is non functioning with the clock then we see
glitches in gated clock signal.
Fig. 2. Latch free clock gating technique
2. LATCH BASED CLOCK GATING
TECHNIQUE:

 It is implemented to solve glitches in latch free based design

because of non functioning of enable signal. Here the enable
signal is controlled by the latch.
Fig. 3. Latch based clock gating technique
 BLOCK DIAGRAM

Fig. 4. ALU with clock gating and operation selection

 TABLE
TABLE – 1
OPCODES FOR VARIOUS INSTRUCTIONS TO ACTIVE
 RESULTS
TABLE – 1
ALU WITHOUT CLOCK GATING
Frequency Static Power Dynamic Power Total Power
(Hz) Dissipation (mw) Dissipation (mw) Dissipation (mw)

100MHz 1294.31 41.75 1336.06

200MHz 1295.87 73.49 1369.36
400MHz 1299 128.62 1427.62
1GHz 1308.26 318.59 1626.85

TABLE – 2
ALU WITH LATCH FREE CLOCK GATING
Frequency Static Power Dynamic Power Total Power
(Hz) Dissipation (mw) Dissipation (mw) Dissipation (mw)

100MHz 1293.47 32.34 1325.81

200MHz 1294.18 64.68 1358.86
400MHz 1295.65 125.44 1423.09
1GHz 1299.96 316.49 1611.45
 TABLE – 3
ALU WITH LATCH BASED CLOCK GATING

Frequency Static Power Dynamic Power Total Power

(Hz) Dissipation (mw) Dissipation (mw) Dissipation (mw)

100MHz 1293.40 29.27 1322.66

200MHz 1294.05 58.53 1352.58
400MHz 1297.04 125.91 1422.95
1GHz 1300.73 309.00 1609.73
 COMPARISION OF RESULTS
COMPARISION OF TOTAL POWER DISSIPATION
1700
1600
T
O 1500

T 1400

A 1300

L 1200
1100
P 1000
O 900
W 800
E 700
R 600
500
400
300
200
100MHz 200MHz 400MHz 1GHz
FREQUENCY
ALU WITHOUT CLOCK GATING ALU WITH LATCH FREE CLOCK GATING ALU WITH LATCH BASED CLOCK GATING
 ADVANTAGES

• Reduced Power Consumption

• Lower Heat Generation
• Extended Battery Life
• Improved Performance
• Dynamic Power Management
• Simplified Design
• Enhanced Reliability
• Cost Savings
 APPLICATIONS

• Mobile Devices
• IoT Devices
• Embedded Systems
• Laptops and Notebooks
• Graphics Processing Units (GPUs)
 CONCLUSION

In conclusion, the use of clock gating in 8-bit ALU design achieves a power efficiency. Usage of
clock gating with PIPO registers gave fast processing and good results. In conclusion, among two
clock gating techniques explored, the Latch Based clock gating technique, combined with PIPO
registers emerged as the most power-efficient design. This project presents a versatile and power
efficient ALU suitable for diverse digital applications.
 FUTURE SCOPE

The application of ALUs with reduced dynamic power dissipation can be widely used in
machine learning, enabling the execution of mathematical operations required for training
and inference in neural networks and other machine learning algorithms, which further
enhances power optimization. ALUs can maintain performance levels with minimized power
consumption even with increased number of operations.
THANK YOU