FULL SCAN DESIGN

Presented By
Praveen Gowda B
M.Tech , VLSI & Embedded Systems
student@MSRIT,Bengaluru
Under the Guidance of
Dr. Deepali Koppad B
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 Contents Of Seminar

▪ Introduction
▪ Typical D Flip-Flop
▪ Scan Flip-Flop (SFF)
▪ Level-sensitive scan design (LSSD)
▪ Scan Design Schematic
▪ Scan Design Rules
▪ Correcting a Rule Violation
▪ Summary 2
 Introduction
⮚The main idea in scan design is to obtain control and observability for flip-flops.
This is done by adding a test mode to the circuit.
⮚All flip-flops functionally form one or more shift registers. The inputs and
outputs of these shift registers (also known as scan registers) are made into
primary inputs and primary outputs.
⮚Thus, using the test mode, all flip-flops can be set to any desired states by
shifting those logic states into the shift register. Similarly, the states of flip-flops
are observed by shifting the contents of the scan register out.
⮚An alternative way of accomplishing the scan function is called random-access
scan (RAS). In that design, flip-flops work as addressable memory elements in
the test mode in a similar fashion as a random access memory (RAM.) This
approach reduces the time of setting and observing the flip-flop states. 3
 Typical D Flip-Flop

⮚ A typical DFF is shown in Figure 14.1.

⮚ Once the circuit is functionally verified, the DFFs are replaced by scan flip-flops
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(SFF).
 Scan Flip-Flop(SFF)

⮚ One typical SFF is shown in Figure 14.2. Here a multiplexer and two new signals,
scan-data SD and test control TC, are added to the D flip-flop (DFF.)
⮚ The original data input D is stored in the flip-flop when TC is 1 and SD is stored
when TC is 0. 5
 Level-sensitive scan design (LSSD)
⮚ Figure 14.3 shows a scan flip-flop with two function clocks, MCK and SCK.
⮚ When MCK is high, data D is latched in the master latch,when SCK is high, the state of
master latch is copied in the slave latch.
⮚ In the scan mode, MCK is held low and scan data SD is latched in by using clocks TCK and
SCK as master and slave clocks, respectively.

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 Scan Design Schematic
⮚ The TCK inputs of all scan flipflops are supplied by a new primary input.
⮚ The SD input of one SFF is supplied by another new primary input SCANIN. All SFFs are
chained by connecting the Q output of one SFF to the SD input of the next SFF.
⮚ The Q output of the last SFF in the chain is a new primary output SCANOUT.
⮚ This design has the advantage of reducing the effort of test generation. Especially for the
case of full-scan, where all flip-flops are scanned, a combinational ATPG program.

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 Scan Design Rules
⮚ R-1: Only D-type master-slave flip-flops should be used. This rule prohibits the use of
other types of flip-flops (JK, toggle, etc.)

⮚ R-2: At least one primary input pin must be available for test. If extra pins are not
available, then any normal primary input can be used as scan-in and any primary output
pin can be multiplexed as scan-out.

⮚ R-3: All flip-flop clocks must be controllable from primary inputs.

⮚ R-4: Clocks must not feed data inputs of flip-flops. A violation of this rule can potentially
lead to a race condition in the normal mode. They capture combinational data in the
normal mode and then carry the data out for observation in the scan mode. The test
procedure relies on the flip-flop correctly capturing data in the normal mode and hence no
race condition is permitted.

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 Correcting a Rule Violation

❖ R-2 Correction This is illustrated in Figure 14.5 where TC (test control) is the only pin
added. Primary input PI2 serves as SCAN IN and primary output pin PO2 also outputs
SCANOUT. Note that the cost of saving these pins is just one extra multiplexer used for
SCANOUT.

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❖ R-3 Correction Here the clock signal (CK) is gated by a combinational signal, D2. Thus,
when D2 = 0, the clock is inhibited and the flip-flop FF retains its state Q. When D2 = 1,
the clock CK stores D1 as the new state.

❖ The clock is applied directly to FF and a multiplexer is added to the combinational logic to
regenerate data for FF. The two circuits are functionally identical and the modified circuit
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satisfies the rule R-3.
 Summary
⮚ Scan is the most popular DFT technique:
• Rule-based design
• Automated DFT hardware insertion
• Combinational ATPG
⮚ Advantages:
• Design automation
• High fault coverage; helpful in diagnosis
• Hierarchical – scan-testable modules are easily combined into large scan-testable systems
• Moderate area (~10%) and speed (~5%) overheads
⮚ Disadvantages:
• Large test data volume and long test time
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• Basically a slow speed (DC) test
THANK YOU
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