ECE3014 Microcontroller Applications

Introduction to ARM – Part 1

 What is an Embedded System?
• An embedded system is a dedicated system designed to perform one or two specific functions.
• It has hardware with software embedded in it as one of its components.
• This system is embedded as a part of a complete device system that includes hardware, such as
electrical and mechanical components.
• The embedded system is unlike the general-purpose computer, which is engineered to manage
a wide range of processing tasks.
• Because an embedded system is engineered to perform certain tasks only, design engineers
may optimize size, cost, power consumption, reliability and performance.
 What Is ARM?
• Advanced RISC Machine

• First RISC microprocessor for commercial use

• Market-leader for low-power and cost-sensitive embedded applications

• The ARM processor is a key component of many successful 32 bit embedded system
ARM Powered Products
 The RISC Design Philosophy
• The ARM core uses a RISC architecture.

• RISC is a design philosophy aimed at delivering simple but powerful

instructions that execute within a single cycle at a high clock speed

• The RISC design philosophy concentrates on reducing the complexity of

instructions performed by the hardware because its easier to provide

greater flexibility and intelligence in software rather than hardware

• Hence, a RISC design places greater demand on the compiler

• Traditional CISC relies more on the hardware for instruction

functionality, and consequently the CISC instructions are more

Figure Courtesy: ARM System Developer’s Guide,
complicated Andrew Sloss
 RISC Vs CISC

RISC CISC
Reduced Instruction Set Computer Complex Instruction Set Computer
Reduced number of instructions Large number of instructions
Single clock cycle instructions Instructions may take several clock cycles
Heavy use of RAM More efficient use of RAM
Emphasis on software Emphasis on hardware
Multiple registers Single register
Low Power Consumption High Power Consumption
Small code size Large code size
Average clock cycle per instruction is 1.5 Average clock cycle per instruction varies between 2 and 15
 The RISC Design Philosophy
The RISC design philosophy is implemented with four major design rules:
• Instructions:
• RISC processors have a reduced number of instruction classes
• These classes provide simple operations that can each execute in a single clock cycle
• The compiler or the programmer synthesizes complex operations (for example, a divide operation)
by combining several simple instructions.
• Each instruction is a fixed length to allow the pipeline to fetch future instructions before decoding
the current instruction
• Pipeline
• The processing of instructions is broken down into smaller units that can be executed in parallel by
pipelines.
• Ideally the pipeline advances by one step on each cycle for maximum throughput
 The RISC Design Philosophy
• Registers:

• RISC machines have a large general purpose register set.

• Any register can contain either data or an address.

• Register act as the fast local memory store for all data processing operations.

• In contrast, CISC processors have dedicated registers for specific purposes.

• Load Store Architecture

• The processor operates on data held in registers.

• Separate load and store instructions transfer data between the register bank and external memory
Over the past few years, ARM has extended its product portfolio by diversifying its CPU development,
which resulted in the new processor family name “Cortex.”
• In this Cortex processor range, the processors are divided into three profiles

• The A profile is designed for high-performance open application platforms.

• The R profile is designed for high-end embedded systems in which real-time performance is needed.
• The M profile is designed for deeply embedded microcontroller-type systems.
 ARM Core Data Flow Model
• A programmer can think of an ARM core as functional units connected
by data buses, as shown in figure
• The arrows represent the flow of data, the lines represent the buses, and
the boxes represent either an operation unit or a storage unit
• Data enters the processor core through the Data Bus. The data may be an
instruction to execute or a data item.
• The instruction decoder, translates the instruction before they are
executed. Each instruction executed belongs to a particular instruction set
• The ARM processor like all RISC processor, uses a Load – Store
Architecture.
• Load instructions copy data from the memory to the registers in the
core
• Store instructions copy data from the registers to memory Figure Courtesy: ARM System Developer’s Guide,
Andrew Sloss
• Data processing is carried out solely in registers.
 ARM Core Data Flow Model
• Data items are placed in the register file – a storage bank made up of
32 bit registers
• ARM is a 32 bit processor, and so most instructions treat registers as
holding signed or unsigned 32 bit values
• ARM instructions typically have two source registers, and , and a
single result of destination register,
• Source operands are read from the register file using the internal
buses A and B respectively.
• The ALU (Arithmetic Logic Unit) and MAC (Multiply – Accumulate
Unit) takes the register values and from the A and B buses and
computes a result.

Figure Courtesy: ARM System Developer’s Guide,

Andrew Sloss
 ARM Core Data Flow Model
• Data processing instructions write the result in directly to the
register file
• Load and store instructions use the ALU to generate an address to be
held in the address register and broadcast on the address bus.
• One important feature of ARM is that the register alternately can be
preprocessed in the barrel shifter before it enters the ALU
• Together the barrel shifter and the ALU can calculate a wide range of
expressions and addresses.
• After passing through the functional units, the result in is written
back to the register file using the Result bus.

Figure Courtesy: ARM System Developer’s Guide,

Andrew Sloss
 r0
ARM Registers
r1 • General purpose registers hold either data or an address
r2
• They are identified with the letter prefixed to the register number.
r3
r4 • The figure shows the active registers available in user mode – a protected mode
r5 normally used when executing applications
r6
• All registers shown are 32 bits in size
r7
r8 • There are upto 18 active registers: 16 data registers and 2 processor status registers.
r9 • The data registers are visible to programmer as to
r10 • The register is traditionally used as the stack pointer (sp) and stores the head of the
r11
r12 stack in the current processor mode
r13 sp • The register is called the link register (lr) and is where the core puts the return
r14 lr address whenever it calls a subroutine
r15 pc
• Register is the program counter (pc) and contains the address of the next instruction
cpsr
- to be fetched by the processor
 ARM Registers
R14: Link Register (LR)
• Used when there is a subroutine call or an interrupt, i.e., branching to a location.
• When a branching becomes necessary, the PC is saved in LR, and PC takes on the new branch address.
• When returning to the original sequence, the PC value can be retrieved from the LR.
• This is a convenient way, because the necessity to push the PC value to stack is avoided.
• The stack is a memory area, and saving and retrieving data from stack is time consuming.
• Having LR to store return addresses, helps to reduce the delay associated with procedure calls and
interrupts
 Current Program Status Register
• The ARM uses the cpsr to monitor and control internal operations
• The cpsr is a dedicated 32 bit register and reside in the register files.

• The cpsr is divided into 4 fields, each 8 –

bits wide: flags, status, extension,
control
• The control field contains the processor
mode, state and the interrupt mask bits.
• The flag field contains the condition
flags. Figure Courtesy: ARM System Developer’s Guide,
Andrew Sloss
 Current Program Status Register
• Condition code flags
• N = Negative result from ALU
• Z = Zero result from ALU
• C = ALU operation Carried out
• V = ALU operation oVerflowed

• Interrupt Disable bits.

• I = 1: Disables the IRQ.
• F = 1: Disables the FIQ.

• T Bit
• Architecture xT only
• T = 0: Processor in ARM state
Figure Courtesy: ARM System Developer’s Guide,
• T = 1: Processor in Thumb state Andrew Sloss

• Mode bits
• Specify the processor mode
 Processor Modes
• The processor mode determines which register are active and the access rights to the cpsr register itself.
• Each processor mode is either privileged or unprivileged
• A privileged mode allows full read – write access to cpsr.
• An unprivileged mode only allows read access to the control field in the cpsr, but still allows read –
write access to the conditional flags
• There are seven modes in total :
• Six privileged modes
• Abort
• Fast interrupt request
• Interrupt request
• Supervisor
• System
• Undefined
• One unprivileged mode
• User
 Processor Modes
• A processor enters the abort mode when there is a failed attempt to access the memory

• Fast interrupt request and interrupt request modes corresponds to two interrupt levels available

on the ARM processor

• Supervisor mode is the mode that the processor is after reset

• System mode is a special version of user mode that allows full read – write access to cpsr.

• Undefined mode is used when the processor encounters an instruction that is undefined or not

supported

• User mode is used for program and applications

 Banked Registers

• Figure shows all 37 registers in the register file

• Of these, 20 registers are hidden from a program
at different times.
• These registers are called banked registers and are
identified by the shading given
• They are available only when the processor in in a
particular mode.
• For example, , , and are banked registers in
abort mode
• Every processor mode except user mode can
change mode by writing directly to the mode bits
of the cpsr.
Figure Courtesy: ARM System Developer’s Guide, Andrew Sloss
 Banked Registers

• Example:
• When the processor is in the interrupt request
mode, the instructions that you execute still
access registers and .
• But these registers are the banked registers
and .
• The user mode registers and are not affected
by the instruction referencing these registers.
• A program has normal access to the other
registers r0 to r12

Figure Courtesy: ARM System Developer’s Guide, Andrew Sloss

 Banked Registers
• Example:
• Figure illustrates what happens when an interrupt forces a
mode change
• The core changes from user mode to interrupt request mode.,
which happens when an interrupt request occurs due to
external device raising an interrupt to the processor core.
• This change causes the user registers r13 and r14 to be
banked.
• The user registers are replaced with r13_irq and r14_irq.
• A new register appears in the interrupt request mode: the
saved program status register (spsr) which stores the
previous mode’s cpsr.
Figure Courtesy: ARM System Developer’s
Guide, Andrew Sloss
 Pipeline
• A pipeline is the mechanism a RISC processor uses to execute instructions.

• Using a pipeline speeds up execution by fetching the next instruction while other instructions are being

decoded and executed.

Fetch Decode Execute

ARM7 three stage pipeline

• Figure shows a three stage pipeline

• Fetch : Loads an instruction from memory

• Decode: Identifies the instruction to be executed

• Execute: Processes the instruction and writes result back to a register

 Pipeline
• Let us illustrate pipelining using an example.

• We will consider three instructions here: ADD, SUB, CMP

Fetch Decode Execute

Cycle 1 ADD
e
Tim

Cycle 2 SUB ADD

Cycle 3 CMP SUB ADD

Thumb-2 Instruction Set Architecture
• The ARMv7-M is the microcontroller profile of the ARMV7 architecture and is different from earlier ARM
architectures in that it supports Thumb-2 instructions alone. Thumb-2 technology is a blend of 16 and 32-
bit instructions that delivers the performance of 32-bit ARM instructions, matches the code density of and
is backwards compatible with, the original 16-bit Thumb instruction set.
• In an ARM7 processor-based system, switching the processor core between the Thumb state for code
density and ARM state for high performance would be necessary for certain applications.
• However, the Cortex-M3 processor does not need to interwork instructions since both 16-bit and 32-bit
instructions co-exist in the same mode, enabling higher code density and performance with far less
complexity.
• As theThumb-2 instructions are a superset of 16-bit Thumb instructions, the Cortex-M3 processor can
execute any previously written Thumb code. By implementing Thumb-2 instructions, the Cortex-M3
processor also delivers compatibility with other members of the ARM Cortex processor family.
Thank You