VLSI DESIGN STYLES

-manoj kumar
 Manoj kumar

ASIC DESIGN TECHNOLOGY OPTIONS

• ASIC is Application specific integrated circuit.
• Any VLSI chips can be designed by using :
1. FULL CUSTOM DESIGN
2. SEMI CUSTOM DESIGN
 Manoj kumar
INTRODUCTION
• Once the synthesizing and testing of circuit is completed in the circuit
design Stage, the subsequent step in the process is physical design of
the circuit.
• In physical design step the circuit description of the components of
the design are transformed into geometric description. This
geometric description, which is used for fabrication of chip is called
integrated circuit layout.
• Several technologies are available for the physical design realization
of a digital circuit. The two major Technology options, to manufacture
the chip from the circuit level to the physical design level are:
– full-custom design
– semi-custom design.
• Full-Custom Design: Designer has full flexibility on the layout design,
no predefined cells are used.
• Semi-Custom Design: Pre-designed library cells are used. Designer
has flexibility in placement of the cells & routing.
 Manoj kumar
FULL CUSTOM
• This is a method of designing integrated circuits. In this method
the function and layout of every single transistor is customized
and optimized by the designer.
• A designer can craft all the circuits by hand this offers freedom to
design different circuit styles and random sizing of transistor.
• Full-custom design increases the performance of the chip
potentially, and minimizes its area, but is very rigorous to
implement.
• Full-custom design is limited to ICs that are to be fabricated in
very high volumes, particularly certain microprocessors and a
small number of ASICs.
• Intel 4004 microprocessor and memory chips are the examples of
full-custom designs. This method is used in early days of digital
era.
 Manoj kumar

• Full custom design is also known as VLSI

design. In full custom design, layout of a mask
is considered primarily.
• Rectangles, polygons were used on mask
levels. This is done manually by the designer.
Photomasks for chips were produced directly
by using material sheets.
• The drawbacks of this approach is that it is
laborious; time consuming and sensitive to
errors.
 Manoj kumar

• Symbolic layout is the modification for mask layout process.

• The primitives like transistors, contacts, wires and ports
(connection points) were used for design instead of
rectangles and polygons.
• Graphics editor is used to manipulate these primitives. The
advantage of this method is that it is possible to transport
layout topologies from process to process with less effort.
• In cell-based design, digital CMOS ICs utilize mask layout
only for high volume parts like microprocessor data paths.
But, in analog and RF designs, cell libraries, memories etc.,
it is mostly used.
• Further, physical layouts were generated by means of
software generators. It is also known as silicon compilation.
 Manoj kumar

• Recent times included different views for the design. For

example, behavioral model, timing view, logic view, circuit
views etc., are needed.
• The software generators automatically provide all the views.
Modern silicon compilers are used to generate memories,
register files etc.
• In this process, not only physical design but also structural
design is captured.
• An HDL function or module call is used to denote circuit
behavior. The advantage is that wire lengths are shortened,
speed and power are improved.
• Full custom design is very expensive for design and production.
Full custom design is mostly preferred from microprocessors or
FPGA than semicustom design. In such designs, high cost of
design is required for large production volumes.
 Manoj kumar

• The advantages of full-custom designs are:

1. High Performance can be attained as the
design is produced from starting point.
2. It can be realized in minimum area.
3. Maximum speed can be attained.
• The disadvantages of full-custom design are:
1. Needs enormous number of staff and labor.
2. Design cost is high.
3. Takes long time for verification and testing.
 Manoj kumar

SEMI CUSTOM DESIGN

• This is an alternative to full-custom design.
• Semi-custom design means a portion of the
design is made/ built with standard logic.
• This method is superior to Full-custom design
with reference to design time, cost, and effort.
• Further, the semi-custom design is partitioned
into several major classes.
 Manoj kumar
Classifications of Semi-custom design
 Manoj kumar

CELL BASED SEMI CUSTOM DESIGN

• In this method the designer uses the cells that have already
been designed and stored in the standard cell library. The
commonly used logic cells are developed using full-custom
design and stored in a standard cell library.
• These cells are designed, verified, and optimized once, and
can be reused several times.
• This reuse property immensely decreases the design cost
and time to market.
• A typical library encompasses one or more AND, OR, and
NOT gates, XOR and XNOR gates and universal gates,
sequential elements (flip-flops), and complex functions like
AND-OR-INVERT, Multiplexer, Full adders, Comparator,
Counter, Decoder, and Encoder.
 Manoj kumar
• The required logic circuits are realized using the
cells in the library. The challenge in this design
is to select the cells and group them to obtain
the required logic.
• The complexity in library composition may
affect area, delay, power consumption, and
dissipation of the circuit.
• Usually, cell-based designs are partitioned into
three classes:
1. Standard Cell-Based Design
2. Compiled Cell-Based Design
3. Macro Cell-Based Design
 Manoj kumar

1. Standard Cell-Based Design:

• In this design method, logic cells are arranged in
rows that are isolated through interconnections (or
routing channels).
• The size of every single logic cell can be different
because of the difference in fan-in of cells.
• The cells arranged in same row must have same
height, but widths can be different Routing
channels are used to connect the cells arranged in
a row.
• The main issue to be addressed in this design
method is interconnection overhead.
 Manoj kumar

2. Compiled Cell-Based Design:

• In this design method, the cells can be
customized and optimized by the designer.
• Cells are produced by a software library tool
according to the parameters supplied by user.
• The cells thus produced are fixed on cell
architecture with predefined technology rules,
like cell size parameters, power budget,
routing style, and contact method.
 Manoj kumar

3.Macro Cell-Based Design:

In Macro Cell-Based Design, macro cells are pre-
designed complex logics, such as multipliers
data paths, memories and DSPs, and embedded
microprocessors.
The functionality and routing within the
module is fixed of flexible.
 Manoj kumar

ARRAY BASED SEMI CUSTOM

• These are alternative to cell-based designs.
• In array based design, the designer is provided with a chip
consisting of configurable logic blocks as generic building
blocks.
• The designer either needs to finish the topmost metallic
interconnect routing to join the different configurable logic
blocks or needs to program the switches on interconnect
by means of electric fields.
• Based on the method employed to configure the logic
blocks the array based design is divided into two classes :
Pre diffused & Pre wired
 Manoj kumar

• Pre-diffused: In this design method, array of

primitive cells are produced by the vendor.
• All the fabrication steps requited to create
these primitive cell are standardized and
optimized.
• With the help of few metallization steps
interconnections are added to the primitive cell
and desired functionality is attained.
• Mask Programmable Gate Arrays is an example
of the pre-diffused design.
 Manoj kumar

• Pre-Wired: In this design method, all the

primitive cells are produced by the vendor.
• These are programmed in the field, that is,
outside the semiconductor foundry.
• The cell encompasses arrays of programmable
modules, each having the capability of
implementing a generic logic function.
• FPGA is an example of pre-wired design.
 Manoj kumar

STANDARD CELL BASED DESIGN

• A standard cell-based ASIC uses pre-designed logic cells
(AND gates, OR gates, multiplexers and flip-flops) known
as standard cells. The use of these cells in ASIC
fabrication is known as a cell-based IC design
methodology.
• The standard cell can be placed anywhere on the silicon,
this means that all the mask layers of a standard cell are
customized and are unique to a particular customer.
• Although the configuration of the cells may be fixed,
their placement in the circuit layout is not limited to a
fixed grid, which enables a design engineer to customize
the layout of the circuit in an optimal fashion.
 Manoj kumar
• The standard-cell areas (also called flexible blocks)
in a CBIC are built-up of rows of standard cells; like
a wall built-up of bricks.
• The standard-cell areas may be used in
combination with larger pre-designed cells,
perhaps microcontrollers or even microprocessors
known as MEGACELLS.
• Mega cells are also called mega functions, full
custom blocks, System-Level Macros (SLMs), fixed
blocks, cores or Functional Standard Blocks (FSBs).
 Manoj kumar

• The designer defines only two things of the

CBIC.
1. The placement of the standard cells.
2. The interconnect in a CBIC.
The standard cells can be placed anywhere
on the silicon. All the mask layers of a CBIC are
customized and are unique to a particular
customer.
 Manoj kumar

Advantages of CBICs
❖ Designers save time and money.
❖ They reduce the risk (by using a pre-designed,
pretested and pre-characterized STANDARD-
CELL library).
❖ Each standard cell can be optimized individually.
❖ During the design of the cell library each and
every transistor in every standard cell can be
chosen to maximize speed or minimize area.
Manoj kumar
 Manoj kumar
• The figure illustrates a cell based (ASIC) CBIC die With a
single standard cell area (i.e., a flexible block) together
with four other fixed blocks.
• The standard cell or the flexible block contains rows of
standard cells.
• The small squares around the edge of the die are
bonding pads that are connected to the pins of the ASIC
package.
• The important features of this type of ASIC are as follows:
1. All mask layers are customized transistors and
interconnect.
2. Custom blocks can be embedded.
3. Manufacturing lead time is about eight weeks.
 Manoj kumar

• Each standard cell in the library is constructed

using full custom design methods, but you can
use these pre-designed and pre-characterized
circuits without having to do any full custom
design yourself.
• This design style gives you the same
performance and flexibility advantages of a
full-custom ASIC but reduces design time and
risk.
 Manoj kumar

• The sequence of operations in a standard cell

based design are:
1. A design is captured using the standard cells
available in a library via schematic or HDL.
2. The layout is then normally automatically placed
and routed by CAD software. (For SSI and MSI
blocks, the layout style is usually identifiable as
rows of constant or near-constant height blocks
separated by rows of routing).
❖ As the complete layout is being done,
optimization of the height of routing channels may
be completed by good placement.
 Manoj kumar

Advantages of Standard Cell-based ASICs

1. By using a pre-designed, pre-tested and pre-characterized

standard cell library, we can save time, money and reduce the
risk.
2. Every transistor in every standard cell can be chosen to
maximize speed or minimize area.
3. No special knowledge of the internal transistor level design of
the cells is required as compared to full custom ASIC.
4. Cell-based implementations generally yield a smaller die size
than would an array-based methodology.
5 These allow more design integration than an array based design
of the same size.
6. Production unit cost may be half that of the equivalent array-
based design.
 Manoj kumar

CHANNELLED GATE ARRAY

• A channelled gate array is shown in figure. The
important characteristics of this type of
masked gate array are:
1. Only a customized interconnect is available.
2. The interconnect uses a predefined space
between the rows of base cells.
3. The manufacturing lead time may vary from
two days to two weeks.
Manoj kumar
 Manoj kumar

• For interconnection, the channelled gate array

uses row of cells separated by the channels
similar to that of cell based (CBIC).

• In a channelled gate array, the spaces

between the rows of cells for interconnection
is fixed in height.
 Manoj kumar

CHANNEL LESS GATE ARRAY

Manoj kumar
 Manoj kumar

• In channel-less gate array, there are no predefined

areas set aside for routing between the cells as in
channelled gate array.
• Thus, the routing is made over the top of gate
array devices. Such routing is possible by the
contact layer (defines the connections between
metal-1, the first layer of metal and transistors)
customization.
• In channel-less array, when an area of transistors
is used for routing, no contact is made with the
devices lying below and the transistors are left
unused.
 Manoj kumar

• Channel-less gate arrays have higher logic

density (i.e., the amount of logic that can be
implemented in a given silicon area) than
channelled gate arrays.
• Similarly, the contact mask in channel-less
gate array is customized but, in channelled
gate array it is not usually customized, which
leads to the increase in density of gate array
cell in channel-less gate array.
 Manoj kumar

FPGA
• A field programmable gate array is a semiconductor
device containing programmable logic components called
'logic blocks' and programmable interconnects.
• Logic blocks can be programmed to perform the function
of basic logic gates such as AND, XOR,OR etc., or more
complex combinational functions such as decoders or
simple mathematical functions.
• In most FPGAs, the logic blocks also include memory
elements, which may be simple flip-flops or more
complete blocks of memory. The generalized structure of
an FPGA is illustrated in figure
Manoj kumar
Manoj kumar
 Manoj kumar

• A hierarchy of programmable interconnects

allows logic blocks to be interconnected as
needed by the system designer.
• Logic blocks and interconnects can be
programmed by the customer or designer
after the FPGA is manufactured to implement
any logical function.
• Hence the name "field-programmable“.
 Manoj kumar
Architecture
The essential elements of an FPGA organized as a 2D
array of cells is illustrated in figure (2).
The typical basic architecture of FPGA consists of:
1. Configurable logic blocks
2. Wiring tracks
3. X-bar switches
4. Input/output pads.
 Manoj kumar
1. Configurable Logic Blocks :
• The generality is the major consideration in the selection
of logic blocks.
• Basically, a two-dimensional array cells are used to
represent logic block.
• Each logic block in an FPGA typically has a smaller
number of inputs and one output.
• A classic FPGA logic block consists of a 4 input look-up
table (LUT) and a flip-flop as shown in figure (3)
 Manoj kumar

• There is only one output, which can be either a

registered or unregistered LUT output.
• The logic block has four inputs for the LUT and a CLK
input for flip-flop.
• The look up table contains storage cells that are used
to implement a small logic function.
• Each cell is capable of holding a single logic value,
either 0 or 1.
• The stored value is produced as the output of the
storage cell.
• The circuit for a two-input LUT is shown in the
following figure (4).
 Manoj kumar

Two Input LUT

 Manoj kumar

2. Wiring Tracks
These wiring tracks are mainly used for routing
signals between cells.
3. X-bar Switches
• These X-bar switches or switch boxes are used
to connect vertical and horizontal wires.
• In the architecture, when a wire enters a switch
box, there are three programmable switches
that allow it to connect to three other wires in
adjacent channel segments.
 Manoj kumar

4. Input / Output Pads

• The input/output pads are used for signal
conditioning at the chip input and output pins.
• These can connect to any one of the wiring
segments in the channels adjacent to it.
Advantages
1. Shorter time to market.
2. Ability to reprogram in the field to fix bugs.
3. Lower non-recurring engineering costs.
 Manoj kumar

Disadvantages
1. FPGAs are slower compared to ASIC counter
parts.
2. They cannot handle complex designs.
3. Consume more power for any semiconductor
process.
 Manoj kumar

APPLICATIONS
• FPGAs can be applied to a very wide range of
applications including, random logic, integrating
multiple SPLDs, device controllers,
communication encoding and filtering small to
medium sized with SRAM blocks and many more.
• Prototyping of designs later to be implemented in
gate arrays .Prototyping might be possible using
only a single large FPGA (which corresponds to a
small gate array in terms of capacity).
 Manoj kumar

• Emulation of entire hardware systems. Emulation

would entail many FPGAs connected by some
sort of interconnect for emulation of hardware,
Quick Turn (and others) have developed products
that comprise many FPGAs and the necessary
software to partition and map circuits.
• Another promising area for FPGA application is
the usage of FPGAs as custom computing
machines. This involves using the programmable
parts to execute software, rather than compiling
the software for execution on a regular CPU.
 Manoj kumar
I/0 pads:

Pad is input if enable anti-fuse is blown to vss ,else output if

blown to vdd
 Manoj kumar

Wiring program
 Manoj kumar

Differences:

Reprogrammable Gate Array Programmable Interconnect Designing

Designing 1. It is an interconnection point
1. It is an extension of between the logic blocks, which
programmable designing. routes signal between input and
2. It can be programmed for many output logic blocks.
times. 2. It can be programmed for only one
3. Example: FPGA (Field time
Programmable Gate Array). 3. Example: Anti-fuse
4. It is classified into two types, they 4. It is classified into two types, they
are, (i) Ad-hoc array , (ii) are, (i) Array based interconnect
Structured array. (ii) Multiplexer based interconnect.
5. This designing technique results 5. The designing of circuit using larger
in iteratively, re-using of the same number of inter-connects results in
chip for new design iterations.
smaller and more efficient modules.
 Manoj kumar
CPLD

• CPLD (Complex Programmable Logic Device) is a PLD with complexity

between that of PAL and FPGA and architectural features of both.
• The building block of a CPLD is the macro cell, which contains logic
implementing disjunctive normal form expressions and more
specialized logic operations.
• They extend the concept of the PLD to a higher level of integration to
improve system performance.
• They also use less board space, improve reliability and reduce cost
instead of making the PLD larger with more inputs, product terms
and macro cells
• A CPLD contains multiple logic blocks, each similar to a small PLD.
• The logic block communicate with one another using signals routed
via a programmable interconnect as shown in figure (1).
• This architectural arrangement makes more efficient use of the
available silicon die area, leading to better performance and reduced
cost.
 Manoj kumar

Fig:1
Manoj kumar
 Manoj kumar

• Most CPLDs use one of two implementations for the

programmable interconnect:
– Array-based or Multiplexer-based interconnect.
• A logic block is similar to a PLD, each has a product-
term array, a product-term distribution scheme and
macro cells.
• The size of the logic block is a measure of its capacity
(how much logic can be implemented in it).
• It is typically expressed in terms of the number of
macro cells, but also important are the number of
inputs to the logic block, the number of product
terms and the product-term distribution scheme.
 Manoj kumar
• Logic blocks usually range in size from 4 to 20
macro cells.
• Sixteen or more macro cells permit 16-bit functions
to be implemented in a single block, provided that
enough inputs from the programmable
interconnect to the logic block exist.
• As with simple PLDs include macro cells that
provide flip-flops and polarity control.
• Polarity enables the implementation of either the
true or complement of an expression — whichever
uses the fewest product terms.
• CPLD macro cells offer more configurability than
PLD macro cells.
 Manoj kumar

Similarities between CPLD and PAL

1. Both CPLD and PAL do not require external
configuration ROM while in case of many
FPGAs it is required. Hence CPU), and PAL can
function immediately on system start-up.
2. As in case of PALs for many legacy CPLDs,
routing constrains most logic blocks to have
input and output signals connected to
external pins, reducing opportunities for
internal state storage and deeply layered logic.
 Manoj kumar

Similarities between CPLD and FPGA

1. A large number of gates are present in both

CPLD and FPGA while in case of PAL the
number of gates are comparatively less.
2. In both CPLD and FPGA, logic which is more
flexible than SOP expressions are provided.
These include complicated feedback paths
between macro cells and specialized logic for
implementing various commonly used
functions like integer arithmetic.
 Manoj kumar

Summary
• The design options to implement a CMOS
system use various (ASICs) Application Specific
Integrated Circuits and programmable logics
as described as follows,
1. Full-custom ASICs
2. Standard-cell based ASCIs
3. Gate array based ASICs.
 Manoj kumar

1. Full Custom ASICs

• Advantages
(i) In the design of full-custom ASICs, all logic cells
are customized by design itself.
(ii) The complete mask design can be redesigned
without use of any library.
(iii) They give best performance.
(iv) For high volume production cost is low.
Disadvantages
(i) They require large time for design.
(ii) Design is complex and hence are expensive.
Example :
Microprocessors are the full-custom ASICs
 Manoj kumar

2. Standard-cell Based ASICs

Advantages already explained in that topic.
Disadvantages
(i) The time and expenses required to design
the cell-library are high.
(ii) Also the time required to manufacture all the
layers of AMC fin new design is high.
Examples: NAND gate, NOR gate, XOR gate,
inverters, buffers, registers and memory devices.
 Manoj kumar

3. Gate Array Based ASICs

The design of gate-array based ASICs use
predefined transistor on the silicon wafer. The
custom masks are used to define the top few
layers of metal which define the interconnection
between transistors.
These ASICs are classified into three types,
(a) Channeled gate arrays
(b) Channel less gate arrays
(c) Structured gate arrays.