Computer Organization and Architecture

(CS304PC)

D.Koteshwar Rao
Assistant Professor,
Department of ECE
 Unit-2

Microprogrammed Control
Control Memory
 The function of the control unit in a digital computer is to
initiate sequences of microoperations.
 When the control signals are generated by hardware, the
control unit is said to be hardwired.
 Microprogramming is a second alternative for designing
the control unit of a digital computer. The principle of
microprogramming is controlling the microoperation
sequences in a digital computer. The control unit initiates a
series of sequential steps of microoperations.
Control Memory
 The control variables at any given time can be represented
by a string of l's and 0's called a control word. control
words can be programmed to perform various operations on
the components of the system.
 A control unit whose binary control variables are stored in
memory is called a Microprogrammed control unit. Each
word in control memory contains a microinstruction.
 Microinstruction specifies one or more microoperations
for the system.
A sequence of microinstructions constitutes a
microprogram.
Control Memory
 A memory that is part of a control unit is referred to as a
control memory. Alterations of the microprogram are not
needed once the control unit is in operation, the control
memory can be a read-only memory (ROM).
 The content of the words in ROM are fixed and cannot be
altered by simple programming since no writing capability
is available in the ROM.
 ROM words are made permanent during the hardware
production of the unit.
Control Memory
 A computer that employs a microprogrammed control unit
will have two separate memories: a main memory and a
control memory.
 Main memory is available to the user for storing the
programs. The contents of main memory may alter when
the data are manipulated and every time that the program is
changed. Main memory consists of machine instructions
and data
Control Memory
 Control memory holds a fixed microprogram that cannot be
altered by the user.
 Microprogram consists of microinstructions that specify
various internal control signals for execution of register
microoperations. Each machine instruction initiates a series
of microinstructions in control memory.
 These microinstructions generate the microoperations to
fetch the instruction from main memory, to evaluate the
effective address, to execute the operation specified by the
instruction.
Control Memory
 The general configuration of a microprogrammed control unit
is demonstrated in the following block diagram.

 Control memory is assumed to be a ROM, within which all

control information is permanently stored.
 Control memory address register specifies the address of the
microinstruction, and the control data register holds the
microinstruction read from memory.
Control Memory
 Microinstruction contains a control word that specifies one or
more microoperations for the data processor. Once these
operations are executed, the control must determine the next
address.
 The location of the next microinstruction may be next in
sequence or it may be located somewhere else in the control
memory.
 Next address is computed in the next address generator circuit and
then transferred into the control address register to read the next
microinstruction.
 Next address generator is sometimes called a microprogram
sequencer, as it determines the address sequence that is read from
control memory. The address of the next microinstruction can be
specified in several ways depending on the sequencer inputs.
Control Memory
 Typical functions of a microprogram sequencer are
incrementing the control address register by one, loading an
address into the control address register from control
memory, transfer an external address or load an initial
address to start the control operations.
 The control data register holds the present microinstruction
while the next address is computed and read from memory.
The data register is sometimes called a pipeline register. It
allows the execution of the microoperations specified by the
control word simultaneously with the generation of the next
microinstruction.
Address Sequencing
 Microinstructions are stored in control memory in groups,
with each group specifying a routine.
 The hardware that controls the address sequencing of the
control memory must be capable of sequencing the
microinstructions within a routine and be able to branch from
one routine to another.
 Steps that the control must undergo during the execution of a
single computer instruction are as follows:
 1. Initial address is loaded into the control address register
when computer is turned ON. This address is the address of
first microinstruction that activates the instruction fetch
routine. The fetch routine may be sequenced by incrementing
the control address register.
Address Sequencing
 The control memory must go through the routine that
determines the effective address of the operand. When the
effective address computation routine is completed, the address
of the operand is available in the memory address register.
 2. The next step is to generate the microoperations that execute
the instruction fetched from memory. The microoperation
depends on the operation code part of the instruction.
 The transformation from the instruction code bits to an address
in control memory where the routine is located is referred to as
mapping process. A mapping procedure transforms the
instruction code into a control memory address.
 When the execution of instruction is completed, control must
return to fetch routine.
Address Sequencing
 Address sequencing capabilities required in a control
memory are:
 1. Incrementing of the control address register.
 2. Unconditional branch or conditional branch, depending
on status bit conditions.
 3. A mapping process from the bits of the instruction to an
address for control memory.
 4. A facility for subroutine call and return
Address Sequencing
 Address Sequencing
 Figure shows block diagram of a control memory and the
associated hardware needed for selecting the next
microinstruction address.
 The microinstruction in control memory contains a set of bits
to initiate microoperations in computer registers and other bits
to specify the method by which the next address is obtained.
The diagram shows four different paths from which the
control address register (CAR) receives the address.
 The incrementer increments the content of the control address
register by one, to select the next microinstruction in sequence.
 Branching is achieved by specifying the branch address in one
of the fields of the microinstruction.
 Address Sequencing
 Conditional branching is obtained by using part of the
microinstruction to select a specific status bit in order to
determine its condition. An external address is transferred
into control memory via a mapping logic circuit.
 The status conditions are special bits in the system that
provide parameter information such as the carry-out of an
adder, the sign bit of a number, the mode bits of an
instruction, and input or output status conditions.
 The return address for a subroutine is stored in a special
register whose value is then used when the microprogram
wishes to return from the subroutine.
 Address Sequencing
 The status bits, together with the field in the microinstruction
that specifies a branch address, control the conditional
branch decisions generated in the branch logic.
 This can be implemented with a multiplexer. Suppose that
there are eight status bit conditions in the system. Three bits
in the microinstruction are used to specify any one of eight
status bit conditions. These three bits provide the selection
variables for the multiplexer.
 An unconditional branch microinstruction can be
implemented by loading the branch address from control
memory into the control address register. This can be
accomplished by fixing the value of one status bit at the input
of the multiplexer to 1.
 Address Sequencing
Mapping of Instruction
 Address Sequencing
Mapping of Instruction
 A simple instruction format as shown in Figure has an operation
code of four bits which can specify up to 16 distinct instructions.
 Assume that the control memory has 128 words, requiring an
address of seven bits. For each operation code there exists a
microprogram routine in control memory that executes the
instruction. One simple mapping process that converts the 4-bit
operation code to a 7-bit address for control memory is shown in
Figure.
 This mapping consists of placing a 0 in the most significant bit of
the address, transferring the four operation code bits and clearing
two least significant bits of the control address register. This
provides for each computer instruction a microprogram routine
with a capacity of four microinstructions.
 Microprogram Example
 Generation of microcode for the control memory is called
microprogramming.
Computer configuration
 The block diagram of the computer is shown in figure. It
consists of two memory units: a main memory for storing
instructions and data, and a control memory for storing the
microprogram.
 Four registers are associated with the processor unit and two
with the control unit.
 The processor registers are program counter PC, address
register AR, data register DR, and accumulator register AC.
 The control unit has a control address register CAR and a
subroutine register SBR.
Microprogram Example
 Microprogram Example
 The transfer of information among the registers in the
processor is done through multiplexers rather than a common
bus.
 DR can receive information from AC, PC, or memory.
 AR can receive information from PC or DR. PC can receive
information only from AR.
 Arithmetic, logic, and shift unit performs microoperations
with data from AC and DR and places the result in AC .
 Memory receives its address from AR. Input data written to
memory come from DR and data read from memory can go
only to DR .
 Microprogram Example
Instruction format
 Computer instruction format consists of three fields: a 1-bit
field for indirect addressing symbolized by I, a 4-bit
operation code (opcode) and a11-bit address field.
 Microprogram Example
Instruction format

 Figure lists four of the 16 possible memory-reference

instructions.
 ADD instruction adds the content of the operand found in the
effective address to the content of AC.
 Microprogram Example
 BRANCH instruction causes a branch to the effective
address if the operand in AC is negative.
 The program proceeds with the next consecutive instruction
if AC is not negative. The AC is negative if its sign bit is 1.
 STORE instruction transfers the content of AC into the
memory word specified by the effective address.
 EXCHANGE instruction swaps the data between AC and the
memory word specified by the effective address.
 Microprogram Example
Microinstruction format
 Microinstruction format for the control memory is shown in
Figure.

 20 bits of the microinstruction are divided into four

functional parts.
 Microprogram Example
Microinstruction format
 The three fields F1, F2, and F3 specify microoperations for
the computer.
 CD field selects status bit conditions. BR field specifies the
type of branch to be used. AD field contains a branch
address.
 The address field is seven bits wide, since the control
memory has 128 = 27 words.
 Microprogram Example
Microoperations
 The microoperations are subdivided into three fields of three
bits each.
 The three bits in each field are encoded to specify seven
distinct microoperations as listed in Table. This gives a total
of 21 microoperations.
 Each microoperation in Table is a register transfer statement.
All transfer-type microoperations symbols use five letters.
The first two letters designate the source register, the third
letter is always a T and the last two letters designate the
destination register.
Microprogram Example
 Microprogram Example
Microoperations
 For example, the microoperation that specifies the transfer
AC DR (F1 = 100)
 has the symbol DRTAC, which stands for a transfer from DR
to AC .
Microprogram Example
 Microprogram Example
Condition field
 CD (condition) field consists of two bits which are encoded
to specify four status bit conditions listed in Table.
 The first condition is always a 1, so that a reference to CD =
00 (or the symbol U) will always find the condition to be
true. When this condition is used in conjunction with the BR
(branch) field, it provides an unconditional branch operation.
 The indirect bit I is available from bit 15 of DR after an
instruction is read from memory.
 The sign bit of AC provides the next status bit.
 The zero value, symbolized by Z, is a binary variable whose
value is equal to 1 if all the bits in AC are equal to zero.
 Microprogram Example
Branch field
 The BR (branch) field consists of two bits. It is used in
conjunction with the address field AD to choose the address of
the next microinstruction.
 When BR = 00, the control performs a jump (JMP) operation
(which is similar to a branch) and when BR = 01, it performs a
call to subroutine (CALL) operation.
 The return from subroutine is accomplished with a BR field
equal to 10. This causes the transfer of the return address from
SBR to CAR
 The mapping from the operation code bits of the instruction to
an address for CAR is accomplished when the BR field is equal
to 11 .
 Design of Control Unit
 The number of control bits that initiate microoperations can
be reduced by grouping mutually exclusive variables into
fields and encoding the k bits in each field to provide 2 k
microoperations.
 Each field requires a decoder to produce the corresponding
control signals. This method reduces the size of the
microinstruction bits but requires additional hardware
external to the control memory.
 It also increases the delay time of the control signals because
they must propagate through the decoding circuits.
Design of Control Unit
Design of Control Unit
Decoding of F fields
 Figure shows three decoders and some of the connections.
 Each of the three fields of the microinstruction presently
available in the output of control memory are decoded with a
3 x 8 decoder to provide eight outputs.
 Each of these outputs must be connected to the proper circuit
to initiate the corresponding microoperation as specified in
above table.
 Outputs 5 and 6 of decoder F1 are connected to the load input
of AR so that either one of these outputs is active,
information from the multiplexers is transferred to AR.
Design of Control Unit
Decoding of F fields
 The multiplexers select the information from DR when output
5 is active and from PC when output 5 is inactive.
 The transfer into AR occurs with a clock pulse transition only
when output 5 or output 6 of the decoder are active.
 The other outputs of the decoders that initiate transfers
between registers must be connected in a similar fashion.
 The other outputs of the decoders that are associated with an
AC operation must also be connected to the arithmetic logic
shift unit in a similar fashion.
Design of Control Unit
Microprogram Sequencer
 The basic components of a microprogrammed control unit are
the control memory and the circuits that select the next address.
The address selection part is called a microprogram sequencer.
 A microprogram sequencer can be constructed with digital
functions to suit a particular application.
 The purpose of a microprogram sequencer is to present an
address to the control memory so that a microinstruction may
be read and executed.
 The next-address logic of the sequencer determines the specific
address source to be loaded into the control address register.
Design of Control Unit
Design of Control Unit
Microprogram Sequencer
 The block diagram of the microprogram sequencer is shown in
Figure. The control memory is included in the diagram to show
the interaction between the sequencer and the memory attached to
it.
 There are two multiplexers in the circuit. The first multiplexer
selects an address from one of four sources and routes it into a
control address register CAR.
 The second multiplexer tests the value of a selected status bit and
the result of the test is applied to an input logic circuit.
 The output from CAR provides the address for the control
memory. The content of CAR is incremented and applied to one
of the multiplexer inputs and to the subroutine register SBR .
Design of Control Unit
Microprogram Sequencer
 The other three inputs to multiplexer number 1 come from the
address field of the present microinstruction, from the output of
SBR, and from an external source that maps the instruction.
 The CD (condition) field of the microinstruction selects one of
the status bits in the second multiplexer. If the bit selected is
equal to 1, the T (test) variable is equal to 1; otherwise, it is
equal to 0.
 Typical sequencer operations are: increment, branch or jump,
call and return from subroutine, load an external address, push
or pop the stack and other address sequencing operations.
Design of Control Unit
Microprogram Sequencer
 The input logic circuit in Figure has three inputs I0, I1 and T,
and three outputs S0, S1 and L. Variables S0 and S1 select one
of the source addresses for CAR. Variable L enables the load
input in SBR.
 The binary values of the two selection variables determine the
path in the multiplexer. With S1S0 = 10, multiplexer input
number 2 is selected and establishes a transfer path from SBR
to CAR
Design of Control Unit
Microprogram Sequencer
Design of Control Unit
Microprogram Sequencer
 The truth table for the input logic circuit is shown in Table.
Inputs I1 and I0 are identical to the bit values in the BR field.
 The truth table can be used to obtain the simplified Boolean
functions for the input logic circuit:
S1 = I1
S0 = I1I0 + I1’T
L = I1’I0T
 The circuit can be constructed with three AND gates, an OR
gate and an inverter.
 Unit-2

Central Processing Unit

Introduction
 A part of the computer that performs bulk data-processing
operations is called central processing unit and is referred to
as the CPU.
 Register set stores intermediate data used during the
execution of the instructions.
 The arithmetic logic unit (ALU) performs the required
microoperations for executing the instructions.
 The control unit supervises the transfer of information among
the registers and instructs the ALU as to which operation to
perform.
Introduction
General Register Organization
 When a large number of registers are included in the CPU, it is
most efficient to connect them through a common bus system.
 The registers communicate with each other not only for direct
data transfers, but also while performing various microoperations.
 Hence it is necessary to provide a common unit that can perform
all the arithmetic, logic and shift microoperations in the processor.
 A bus organization for seven CPU registers is shown in Figure.
The output of each register is connected to two multiplexers
(MUX) to form the two buses A and B.
 The selection lines in each multiplexer select one register or the
input data for the particular bus.
General Register Organization
 A and B buses form the inputs to a common arithmetic logic
unit (ALU). The operation selected in the ALU determines the
arithmetic or logic microoperation that is to be performed.
 The result of the microoperation is available for output data and
also goes into the inputs of all the registers.
 The register that receives the information from the output bus is
selected by a decoder.
 The decoder activates one of the register load inputs, thus
providing a transfer path between the data in the output bus and
the inputs of the selected destination register.
 The control unit that operates the CPU bus system directs the
information flow through the registers and ALU by selecting
various components in the system.
General Register Organization
 Example: R1 R2 + R3
 1. MUX A selector (SELA): to place the content of R2 into
bus A.
 2. MUX B selector (SELB): to place the content of R3 into
bus B.
 3. ALU operation selector (OPR): to provide the arithmetic
addition A + B .
 4. Decoder destination selector (SELD): to transfer the
content of the output bus into R1.
General Register Organization
Control word:
 The 14-bit control word is shown in the figure. It consists of four
fields. Three fields contain three bits each and one field has five
bits.
 The three bits of SELA select a source register for the A input of
the ALU. The three bits of SELB select a register for the B input
of the ALU. The three bits of SELD select a destination register
using the decoder and its seven load outputs.
 The five bits of OPR select one of the operations in the ALU.
General Register Organization
General Register Organization
 The encoding of the register selections is specified in Table.
 The 3-bit binary code listed in the first column of the table
specifies the binary code for each of the three fields. The
register selected by fields SELA, SELB, and SELD is the one
whose decimal number is equivalent to the binary number in
the code.
 When SELA or SELB is 000, the corresponding multiplexer
selects the external input data. When SELD = 000, no
destination register is selected.
General Register Organization
General Register Organization
Examples of Microoperations
R1 R2 - R3
Field: SELA SELB SELD OPR
Symbol: R2 R3 R1 SUB
Control word: 010 011 001 00101
General Register Organization
Stack Organization
 A stack is a storage device that stores information in such a
manner that the item stored last is the first item retrieved (LIFO).
 The stack in digital computers is essentially a memory unit with
an address register that can count only after an initial value is
loaded into it.
 The register that holds the address for the stack is called a stack
pointer (SP).
 The two operations of a stack are the insertion and deletion of
items.
 The operation of insertion is called push (pushing a new item on
top). The operation of deletion is called pop (removing one item).
 These operations are simulated by incrementing or decrementing
the stack pointer register.
Stack Organization
Stack Organization
Register stack
 Figure shows the organization of a 64-word register stack.
The stack pointer register SP contains a binary number whose
value is equal to the address of the word.
 Three items are placed in the stack: A, B and C. Item C is on
top of the stack so that the content of SP is now3.
 To remove the top item, the stack is popped by reading the
memory word at address 3 and decrementing the content of
SP . Item B is now on top of the stack since SP holds address
2.
 To insert a new item, the stack is pushed by incrementing SP
and writing a word in the next-higher location in the stack.
Stack Organization
Register stack
 In a 64-word stack, the stack pointer contains 6 bits because 2 6
= 64.
 When 63 is incremented by 1, the result is 0 since 111111 + 1
= 1000000 in binary, but SP can accommodate only the six
least significant bits.
 Similarly, when 000000 is decremented by 1, the result is
111111.
 The one-bit register FULL is set to 1 when the stack is full, and
the one-bit register EMTY is set to1 when the stack is empty.
 DR is the data register that holds the binary data to be written
into or read out of the stack.
Stack Organization
Register stack
 The push operation is implemented with the following
sequence of microoperations;
SP SP + 1 Increment stack pointer
M [SP] DR Write item on top of the stack
If (SP=0) then (FULL 1) Check if stack is full
EMTY 0 Mark the stack not empty
Stack Organization
Register stack
 The pop operation consists of the following sequence of
microoperations:
DR M [SP] Read item from the top of stack
SP SP – 1 Decrement stack pointer
If (SP=0) then (EMTY 1) Check if stack is empty
FULL 0 Mark the stack not full
Stack Organization
Memory Unit
Address

2000

Stack grows
in this
direction

DR
Stack Organization
Memory stack
 Figure shows a portion of computer memory partitioned into
three segments: program, data, and stack.
 The program counter PC points at the address of the next
instruction in the program. The address register AR points at
an array of data.
 Stack pointer SP points at the top of the stack. The three
registers are connected to a common address bus and either
one can provide an address for memory. PC is used during the
fetch phase to read an instruction. AR is used during the
execute phase to read an operand. SP is used to push or pop
items into or from the stack.
Stack Organization
Memory stack
 A new item is inserted with the push operation as follows:
SP SP - 1
M[SP] DR
 A new item is deleted with a pop operation as follows:
DR M[SP]
SP SP + 1
Stack Organization
Reverse Polish Notation
 Consider the simple arithmetic expression A*B+C*D
 The Polish mathematician Lukasiewicz showed that arithmetic
expressions can be represented in prefix or polish notation, places
the operator before the operands.
 The postfix notation, referred to as Reverse Polish notation (RPN),
places the operator after the operands.
 The following examples demonstrate the three representations:
A + B Infix notation
+ AB Prefix or Polish notation
AB + Postfix or reverse Polish notation
 The expression is written in reverse Polish notation as AB * CD *
+
 In reverse polish notation ,
34*56*+

•The advantage of memory stack is that the CPU can refer to

SP without having to specify an address, since address is
available in SP
Instruction Formats
 The most common fields found in instruction formats are:
1. An operation code field that specifies the operation to be
performed.
2. An address field that designates a memory address or a
processor register.
3. A mode field that specifies the way the operand or the effective
address is determined.
 Operations specified by computer instructions are executed on
some data stored in memory or processor registers.
 Operands residing in memory are specified by their memory
address.
 Operands residing in processor registers are specified with a
register address.
Instruction Formats
 The number of address fields in the instruction format of a
computer depends on the internal organization of its registers.
 Most computers fall into one of three types of CPU
organizations:
1. Single accumulator organization.
2. General register organization.
3. Stack organization.
 The instruction format in single accumulator organization
type of computer uses one address field. For example,
ADD X
 where X is the address of the operand. The ADD instruction
in this case results in the operation AC AC + M [X].
Instruction Formats
 The instruction format in general register organization type of
computer needs three register address fields. The instruction for
an arithmetic addition may be written in an assembly language as
ADD R1, R2, R3
 denote the operation R1 R2 + R3.
 The number of address fields in the instruction can be reduced from
three to two. Thus the instruction
ADD R1, R2
 would denote the operation R1 R1 + R2.
 Instruction with a mnemonic MOV used to symbolize a transfer
instruction. Thus the instruction
MOV R1, R2
 denotes the transfer R1 R2 or R2 R 1
Instruction Formats
 An instruction symbolized by
ADD R1, X
 would specify the operation R1 R1 + M [X]. It has two address
fields, one for register R1 and the other for the memory address X.
 Computers with stack organization would have PUSH and POP
instructions which require an address field. Thus the instruction
PUSH X
 will push the word at address X to the top of the stack. These
instructions do not need an address field.
 The instruction
ADD
 in a stack computer consists of an operation code only with no
address field.
Instruction Formats
 Evaluate the arithmetic statement X = (A + B) * (C + D)
using zero, one, two or three address instructions.
Three-Address Instructions:
 Computers with three-address instruction formats can use
each address field to specify either a processor register or a
memory operand.
ADD R1, A, B R1 M [ A ] + M [ B ]
ADD R2, C, D R2 M [ C ] + M [ D ]
MUL X, R1, R2 M [ X ] R1 * R2
 Advantage: Short Program
 Disadvantage:binary-coded inst requires too many bits
Instruction Formats X = (A + B) * (C +
D)
Two-Address Instructions:
MOV R1, A R1 M [ A ]
ADD R1, B R1 R1 + M [ B ]
MOV R2, C R2 M [ C ]
ADD R2, D R2 R2 + M [ D ]
MUL R1, R2 R1 R1 * R2
MOV X, R1M [ X ] R1
Instruction Formats
One-Address Instructions: X = (A + B) * (C + D)
 One-address instructions use an implied accumulator (AC) register
for all data manipulation. For multiplication and division there is a
need for a second register. However, here we will neglect the second
register and assume that the AC contains the result of all operations.
LOAD A AC M [ A ]
ADD B AC AC + M [ B ]
STORE T M[T] AC
LOAD C AC M [ C ]
ADD D AC AC + M [ D ]
MUL T AC AC * M [ T ]
STORE X M[X] AC
 T is the address of temporary memory location for storing the
intermediate result
Instruction Formats
Zero-Address Instructions: X = (A + B) * (C + D)
 A stack-organized computer does not use an address field for the
instructions ADD and MUL. PUSH and POP instructions need an
address field to specify the operand that communicates with the
stack. TOS stands for top of stack.
PUSH A TOS A
PUSH B TOS B
ADD TOS (A + B)
PUSH C TOS C
PUSH D TOS D
ADD TOS (C + D)
MUL TOS (C + D) * (A + B)
POP X M[X] TOS
 The name "zero-address” is given to this type of computer because
of the absence of an address field in the computational instructions.
Instruction Formats
RISC Instructions: X = (A + B) * (C +
D)
 A program for a RISC-type CPU consists of LOAD and STORE
instructions that have one memory and one register address, and
computational-type instructions that have three addresses with all
three specifying processor registers.
LOAD R1, A R1 M [ A ]
LOAD R2, B R2 M [ B ]
LOAD R3, C R3 M [ C ]
LOAD R4, D R4 M [ D ]
ADD R1, R1, R2 R1 R1 + R2
ADD R3, R3, R4 R3 R3 + R4
MUL R1, R1, R3 R1 R1 * R3
STORE X, R1 M[X] R1
Instruction Formats
 The load instructions transfer the operands from memory to
CPU registers.
 The add and multiply operations are executed with data in the
registers without accessing memory
Addressing Modes
 The addressing mode specifies a rule for interpreting or
modifying the address field of the instruction before the
operand is actually referenced.
 An example of an instruction format with a distinct
addressing mode field is shown in Figure. The mode field is
used to locate the operands needed for the operation. Address
field designate a memory address or a processor register.

 There are two modes that need no address field at all. These
are the implied and immediate modes.
Addressing Modes
Implied Mode:
 In this mode, the operands are specified implicitly in the
definition of the instruction.
 For example, the instruction "complement accumulator” is
an implied-mode instruction because the operand in the
accumulator register is implied in the definition of the
instruction.
 All register reference instructions that use an accumulator are
implied-mode instructions.
 Zero-address instructions in a stack-organized computer are
implied-mode instructions since the operands are implied to
be on top of the stack.
Addressing Modes
Immediate Mode:
 In this mode, the operand is specified in the instruction itself.
 In other words, an immediate-mode instruction has an
operand field rather than an address field.
Register Mode:
 In this mode, the operands are in registers that reside within
the CPU.
 A particular register is selected from a register field in the
instruction. k-bit field can specify any one of 2k registers.
Addressing Modes
Register Indirect Mode:
 In this mode, the instruction specifies a register in the CPU
whose contents give the address of the operand in memory.
 In other words, the selected register contains the address of
the operand rather than the operand itself.
 The advantage of a register indirect mode instruction is that
the address field of the instruction uses fewer bits to select a
register than would have been required to specify a memory
address directly.
Addressing Modes
Autoincrement or Autodecrement Mode:
 This is similar to the register indirect mode except that the
register is incremented or decremented after or before its value
is used to access memory.
Direct Address Mode:
 In this mode, the effective address is equal to the address part of
the instruction. The operand resides in memory and its address is
given directly by the address field of the instruction.
Indirect Address Mode:
 In this mode, the address field of the instruction gives the
address where the effective address is stored in memory. Control
fetches the instruction from memory and uses its address part to
access memory again to read the effective address.
Addressing Modes
Relative Address Mode:
 In this mode, the content of the program counter is added to the
address part of the instruction in order to obtain the effective
address.
 The address part of the instruction is usually a signed number (in
2's complement representation) which can be either positive or
negative. When this number is added to the content of the program
counter, the result produces an effective address.
Indexed Addressing Mode:
 In this mode, the content of an index register is added to the
address part of the instruction to obtain the effective address.
 The index register is a special CPU register that contains an index
value. The address field of the instruction defines the beginning
address of a data array in memory
Addressing Modes
Base Register Addressing Mode:
 In this mode, the content of a base register is added to the
address part of the instruction to obtain the effective address.
 This is similar to the indexed addressing mode except that the
register is now called a base register instead of an index
register.
 An index register is assumed to hold an index number that is
relative to the address part of the instruction.
 A base register is assumed to hold a base address and the
address field of the instruction gives a displacement relative
to this base address.
Addressing Modes
Numerical Example:
Addressing Modes
Numerical Example:
Data Transfer and Manipulation
 Most computer instructions can be classified into three
categories:
1. Data transfer instructions
2. Data manipulation instructions
3. Program control instructions
 Data transfer instructions cause transfer of data from one
location to another without changing the binary information
content.
 Data manipulation instructions are those that perform
arithmetic, logic and shift operations.
 Program control instructions provide decision-making
capabilities and change the path taken by the program when
executed in the computer.
Data Transfer Instructions
 Data transfer instructions move data from one place in the
computer to another without changing the data content.
 The most common transfers are between memory and
processor registers, between processor registers and input or
output, and between the processor registers themselves.
 Table gives a list of eight data transfer instructions used in
many computers.
Data Transfer Instructions
 LOAD instruction designates a transfer from memory to a
processor register, usually an accumulator.
 STORE instruction designates a transfer from a processor
register into memory.
 MOVE instruction designate a transfer from one register to
another.
 EXCHANGE instruction swaps information between two
registers or a register and a memory word.
 INPUT and OUTPUT instructions transfer data among
processor registers and input or output terminals.
 PUSH and POP instructions transfer data between processor
registers and a memory stack.
Data Transfer Instructions
Data Transfer Instructions
 Table shows the recommended assembly language
convention and the actual transfer accomplished in each case.
Load instruction can occur with eight different addressing
modes.
 ADR stands for an address, NBR is a number or operand, X is
an index register, R1 is a processor register and AC is the
accumulator register.
Data Transfer Instructions
 @ character symbolizes an indirect address. $ character
before an address makes the address relative to the program
counter PC. # character precedes the operand in an
immediate-mode instruction. An indexed mode instruction is
recognized by a register that is placed in parentheses after the
symbolic address.
 The register mode is symbolized by giving the name of a
processor register. In the register indirect mode, the name of
the register that holds the memory address is enclosed in
parentheses.
 Autoincrement mode is distinguished from the register
indirect mode by placing a plus after the parenthesized
register. Autodecrement mode would use a minus instead.
Data Manipulation Instructions
 Data manipulation instructions perform operations on data.
Data manipulation instructions in a typical computer are
usually divided into three basic types:
1. Arithmetic instructions
2. Logical and bit manipulation instructions
3. Shift instructions
Data Manipulation Instructions
Data Manipulation Instructions
 The four basic arithmetic operations are addition, subtraction,
multiplication and division. A list of typical arithmetic
instructions is given in Table.
 The increment instruction adds 1 to the value stored in a
register or memory word.
 The instruction "add with carry" performs the addition on two
operands plus the value of the carry from the previous
computation.
 Similarly, the "subtract with borrow" instruction subtracts
two words and a borrow which may have resulted from a
previous subtract operation.
 The negate instruction forms the 2' s complement of a
number.
Data Manipulation Instructions
Data Manipulation Instructions
 Individual bits such as a carry can be cleared, set or
complemented with appropriate instructions.
 Another example is a flip-flop that controls the interrupt
facility and is either enabled or disabled by means of bit
manipulation instructions.
Data Manipulation Instructions
Data Manipulation Instructions
 Individual Shifts are operations in which the bits of a word
are moved to the left or right.
 The bit shifted in at the end of the word determines the type
of shift used.
 Shift instructions may specify either logical shifts, arithmetic
shifts or rotate-type operations.
 The rotate through carry instruction treats a carry bit as an
extension of the register whose word is being rotated.
 A rotate-left through carry instruction transfers the carry bit
into the rightmost bit position of the register, transfers the
leftmost bit position into the carry and at the same time, shifts
the entire register to the left.
Program Control
 A program control type of instruction when executed, may
change the address value in the program counter and cause
the flow of control to be altered. In other words, program
control instructions specify conditions for altering the content
of the program counter, while data transfer and manipulation
instructions specify conditions for data-processing operations.
 The change in value of the program counter as a result of the
execution of a program control instruction causes a break in
the sequence of instruction execution.
 This is an important feature in digital computers as it provides
control over the flow of program execution and a capability
for branching to different program segments.
Program Control
Program Control
 Some typical program control instructions are listed in Table.
 Branch and jump instructions are used interchangeably to mean the
same thing but sometimes they are used to denote different
addressing modes.
 Branch instruction causes a transfer of the value of ADR into the
program counter. Branch and jump instructions may be conditional
or unconditional.
 The skip instruction does not need an address field and is therefore
a zero-address instruction.
 The call and return instructions are used in conjunction with
subroutines.
 Compare instruction performs a subtraction between two operands.
 Test instruction performs the logical AND of two operands.