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8259 Programmable Interrupt Controller

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28 views10 pages

8259 Programmable Interrupt Controller

Uploaded by

Nandu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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8259 Programmable Interrupt

Controller
Block Diagram
Block Diagram description
• Interrupt Request Register (IRR) and In-
Service Register (ISR)
• The interrupts at the IR input lines are handled
by two registers in cascade, the Interrupt
Request Register (lRR) and the In- Service
Register (lSR). The IRR is used to indicate all the
interrupt levels which are requesting service,
and the ISR is used to store all the interrupt
levels which are currently being serviced
• Priority Resolver
• This logic block determines the priorities of
the bits set in the lRR. The highest priority is
selected and strobed into the corresponding
bit of the lSR during the INTA sequence.
• Interrupt Mask Register (IMR)
• The lMR stores the bits which disable the
interrupt lines to be masked. The IMR
operates on the output of the IRR. Masking of
a higher priority input will not affect the
interrupt request lines of lower priority.
• Data Bus Buffer
• This 3-state, bidirectional 8-bit buffer is used to interface the PIC to
the System Data Bus. Control words and status information are
transferred through the Data Bus Buffer.
 Read/Write Control Logic
 The function of this block is to accept output commands from the
CPU. It contains the Initialization Command Word (lCW) registers
and Operation Command Word (OCW) registers which store the
various control formats for device operation. This function block
also allows the status of the PIC to be transferred onto the Data
Bus. This function block stores and compares the IDs of all PICs
used in the system. The associated three I/O pins (CAS0- 2) are
outputs when the 8259 is used as a master and are inputs when the
8259 is used as a slave. As a master, the 8259 sends the ID of the
interrupting slave device onto the CAS0 - 2 lines. The slave, thus
selected will send its preprogrammed subroutine address onto the
Data Bus during the next one or two consecutive INTA pulses.
• D[7..0] These wires are connected to the system bus and are used by the
microprocessor to write or read the internal registers of the 8259.
• A[0..0] This pin acts in conjunction with WR/RD signals. It is used by the
8259 to decipher various command words the microprocessor writes and
status the microprocessor wishes to read.
 WR When this write signal is asserted, the 8259 accepts the
command on the data line, i.e., the microprocessor writes to the 8259
by placing a command on the data lines and asserting this signal.
 RD When this read signal is asserted, the 8259 provides on the
data lines its status, i.e., the microprocessor reads the status of the
8259 by asserting this signal and reading the data lines.
 INT This signal is asserted whenever a valid interrupt request is
received by the 8259, i.e., it is used to interrupt the microprocessor.
 INTA This signal, is used to enable 8259 interrupt-vector data
onto the data bus by a sequence of interrupt acknowledge pulses
issued by the microprocessor.
 IR 0,1,2,3,4,5,6,7 An interrupt request is executed by a
peripheral device when one of these signals is asserted.
 CAS[2..0] These are cascade signals to enable multiple 8259
chips to be chained together.
 SP/EN This function is used in conjunction with the CAS signals for
cascading purposes
Priority Modes
• Fully Nested mode: All IRs are arranged in
from lowest to highest priority.
• Automatic Rotation mode: In this mode, a
device after being served assumes the lowest
priority.
• Specific Rotation mode: This mode is same as
ARM except that the user can select any IR for
the lowest priority.
End of Interrupt
• Non Specific EOI Command: it resets the
highest priority ISR bit.
• Specific EOI Command: This command
specifies which ISR bit to reset.
• Automatic EOI Command: In this, the ISR bit is
reset after the third INTA.
Initialization command words(ICWs)
• ICW1 and ICW2

0 A7 A6 A5 1 LTIM ADI SNGL IC4 ICW1

A15 A14 A13 A12 A11


1 / T7 / T6 / T5 / T4 / T3
A10 A9 A8 ICW2

LTIM (1 = Level-Triggered Interrupt Mode, 0 = Edge-Triggered Interupt


Mode) ADI is length of Address-Interval for call-instruction (1 = 4-bytes, 0
= 8-bytes) SNGL (1 = single controller system, 0 = multiple controllers in
cascade mode) IC4 means Initialization Command-Word 4 is needed (1 =
yes, 0 = no)

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