DIGITAL SYSTEM DESIGN : An Introduction

Dr. Kanika Sharma

Assistant Professor, ECE Deptt.,
NITTTR
 Programmable Logic

• These are the devices with,

– Programmable Interconnects.
– Large number of flip-flops.
– Large number of logic gates.

• Here memory cells controls the functionality

through programmable interconnects.

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 Advantages of Programmable Logic

• Saves valuable board space and debug time.

• Includes a security fuse that can be used to protect IP.

• Requires Less switching current and switching o/ps.

• Faster time to market.

• Less NRE cost with more logic flexibility.

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 Programmable Logic Devices
• They were introduced in the 1970s.
• The function provided by each of the 7400-series parts is fixed
and cannot be tailored to suit a particular design situation.
• So it is possible to manufacture chips that contain relatively
large amounts of logic circuitry with a structure that is fixed.
• A PLD is a general- purpose chip for implementing logic
circuitry. It contains a collection of logic circuit elements that
can be customized in different ways
• It can be viewed as a black box, that contains logic gates and
programmable switches.
 Logic gates
Inputs and Outputs
(logic variables) programmable (logic functions)
switches

Figure 3.24. Programmable logic device as a black box.

 Types of Programmable Logic
• Simple Programmable Logic Devices(SPLDs)

• Complex Programmable Logic Devices(CPLDs)

• Field Programmable Gate Arrays(FPGAs)

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 SPLDs
• SPLDs are simple programmable logic devices like,
– PLA : Programmable Logic Array.
• Contains AND and OR array.
• AND array infers Product Terms for I/p variables.
• OR array makes ORing of product terms to form output
functions.

– PAL : Programmable Array Logic

• Here AND array is programmable and OR array is fixed.

– GAL : Generic Array Logic.

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 CPLDs
• These are having some higher logic capacity than SPLDs.
– One typical CPLD may be equivalent to 2 to 64 SPLDs.
– The development languages of most of the CPLDs and SPLDs are
same like ABEL,CuPL,PALASM etc.

• Some of the CPLDs are,

– EPLD – Erasable Programmable Logic Device.
– PEEL – Programmable Electrically Erasable Logic.
– EEPLD – Electrically Erasable Programmable Logic Device.
– MAX – Multiple Array Matrix of Altera.

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 CPLDs
• CPLD microcells consists of different Logic Blocks
interconnected together via a programmable Switch matrix.

• A Function Block contains a group of 8 to 10 microcells

grouped together.

• CPLD uses a non-volatile memory cells such as

EPROM,EEPROM,FLASH.

• In circuit Programmability can be achieved by using ISP feature

of CPLDs. (I.e. In System Programmable)

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 FPGAs
• FPGAs are having
– an internal array of Logic Blocks.
– Surrounded ring of I/O Blocks.
– Programmable Interconnects.

• These are also known as ,

– LCA – Logic Cell Array.
– ACT – Actel
– FLEX,APEX – Altera
– pASIC – Programmable ASICs-QuickLogic.
– Virtex – XILINX
– ORCA - Lucent

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 FPGA Classification
• FPGAs are classified according to their Architecture as,
– Coarse Grained
– Fine Grained

• Coarse Grained Architectures are consists of some fixed high

performance logic blocks like ALUs, registers, multipliers.
Ex. Atmel (AT 40K),Altera (FLEX).

• Fine Grained Architectures are consists of Small Local

Memories
Ex. Actel ACT FPGAs.

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 Manufacturing Technologies
• Most FPGAs use SRAM or Anti-Fuse CMOS Technology.

– SRAM based FPGAs are programmable.

– Anti-Fused based FPGAs are one time programmable.

• In SRAM technology Configuration Memory has a program in

it that defines
– The function of each logic block
– Which blocks are I/ps and which are o/ps.
– Interconnects between blocks.

• In anti-fuse technology, a programming current of 5 mA

blows an anti-fuse to make a permanent connection.

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JOINT TEST ACTION GROUP
(JTAG)
• For connection of CPLD with PC, a small connector
is included on the PCB that houses the CPLD, and
a cable is connected between that connector and
computer system.
• The CPLD is programmed by transferring the
programming information generated by a
CAD/VHDL system through the cable, from the
computer into the CPLD.
• The circuitry on the CPLD that allows this type of
programming has been standardized by the IEEE
and is usually called a JTAG port.
• It uses 4 wires to transfer information between
the computer and the device being programmed.
 (a) CPLD in a Quad Flat Pack (QFP) package

To computer

Printed
circuit board

(b) JTAG programming

Figure 3.34. CPLD packaging and programming.

ISP

In system Programmable (ISP):

Means The ability to reconfigure

the logic & Functionality of a device.

This can be done before,after or

during the manufacture.

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 ISP Features & Advantages
• Features of ISP :
– Flexible and easy to modify hardware.
– Design Up gradation is simple.
– No special manufacturing flow is required.
– 20-year program retention ability.
– A minimum 10,000 program-erase cycles.

• Advantages of ISP :
– Faster time to market.
– Internal test and board reconfiguration.
– Superior prototyping with multi function h/w designs.
– Security feature allowing density security, I.e. A secured
device can not be read back until it has been erased.

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SPLDs
PROGRAMMABLE LOGIC ARRAY
(PLA)
 Programmable Logic Array
• The first developed PLD was PLA.
• Based on the idea that logic functions can be
realized in sum-of-products form, a PLA
comprises a collection of AND gates that feeds
a set of OR gates.
 x1 x2 xn

Input buffers
and
inverters

x 1 x1 xn xn

P1

AND plane OR plane

Pk

f1 fm

Figure 3.25. General structure of a PLA.

 x1 x2 x3

Programmable
connections

OR plane
P1

P2

P3

P4

AND plane

f1 f2
Figure 3.26. Gate-level diagram of a PLA.
Find out P1, P2, P3, P4, f1, f2
From the diagram
P1 = x1x2 , P2 = x1x3 (bar) ,
P3 = x1(bar)x2(bar)x3 ,
P4 = x1x3
f1 = x1x2 + x1x3 (bar) + x1(bar)x2(bar)x3
f2 = x1x2 + x1x3 + x1(bar)x2(bar)x3
• Commercially available PLAs come in larger sizes
than this.
• Typical parameters are 16 inputs, 32 product
terms, and eight outputs
• In above slide , each AND gate is depicted as a
single horizontal line attached to an AND- gate
symbol.
• The possible inputs to the AND gate are drawn as
vertical lines that cross the horizontal line.
• At any crossing of a vertical and horizontal line, a
programmable connection, indicated by an X, can
be made.
x1 x2 x3

OR plane
P1

P2

P3

P4

AND plane

f1 f2
PROGRAMMABLE ARRAY LOGIC
(PAL)
 Programmable array Logic
• In this AND array is programmable and OR
array is fixed
• They are simple to manufacture, and less
expensive than PLAs and offer better
performance.
x1 x2 x3

P1

f1
P2

P3

f2
P4

AND plane

Figure 3.28. An example of a PAL

Find out P1, P2, P3, P4, f1, f2
• The PAL is programmed to realize the two
logic functions,
f1 = x1x2 x3(bar)+ + x1(bar)x2x3
f2 = x1(bar)x2 (bar)+ x1x2x3
EXTRA CIRCUITRY RESULTS IN
MACROCELL
 Extra Circuitry added to OR gate
• In many PALs extra circuitry is added at the
output of each OR gate to provide additional
flexibility.
• The term macrocell to refer to the OR gate
combined with the extra circuitry.
 Select
Enable

f1
Flip-flop

D Q

Clock

To AND plane

Figure 3.29. Extra circuitry added to OR-gate from Figure 3.28.

• A 2:1 multiplexer selects as an output from the
PAL either the or- gate output or the flip-flop
output.
• The multiplexer select line can be programmed to
be either 0 or 1.
• A tri state buffer, connected between the
multiplexer and the pal output.
• Finally the multiplexer’s output is fed back to the
AND plane in the PAL This connection allows the
implementation of logic circuits that have multiple
stages.
COMPLEX PROGRAMMABLE LOGIC
DEVICES
• High Performance
Features
– 5ns Pin to pin delays on all pins
• Large density range
– 36 to 288 macro cells with 800 to 6400 usable gates
• 5 V in system programmable
– Endurance of 10,000 program/erase cycles.
– Program/erase over full commercial voltage and temperature range.
• Enhanced pin-locking architecture
• Flexible 36V18 function Block.
– 90 product terms drive any 18 macrocells within function block.
– Global and product term clocks, output enables, set and reset signals.
• Slew rate control on individual outputs.
• User programmable ground pin capability
• Advanced CMOS 5V FastFlash technology.
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• For implementation of circuits that require
more inputs & outputs, either multiple
PLAs or PALs can be employed or else a
sophisticated type of chip, called a complex
programmable logic device (CPLD), can be
used.
• A CPLD comprises circuit blocks on a single
chip, with internal wiring resources to
connect the circuit blocks.
 I/O block

I/O block
PAL-like PAL-like
block block

Interconnection wires
I/O block

I/O block
PAL-like PAL-like
block block

Figure 3.32. Structure of a complex programmable logic device (CPLD).

WIRING STRUCTURE WITH CPLD
 PAL-like block (details not shown)

PAL-like block

D Q

D Q

D Q

Figure 3.33. A section of the CPLD in Figure 3.32.

• The interconnection wiring contains
programmable switches that are used to connect
the PAL- like blocks.
• Extensive research has been done to decide how
many switches should be provided for
connections between the wires.
• The no. of switches is chosen such that sufficient
flexibility provided
• When a pin is used an input, the macro cell
associated with that pin cannot be used and
therefore wasted.
• CPLDs usually support the ISP feature.
XC9500 in system Programmable
CPLD Family

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 CPLDs
Small number of largish PLDs (e.g., “36V18”) on a single chip.
Programmable interconnect between PLDs

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 CPLD families
• Identical individual PLD blocks (Xilinx “FBs”) replicated in
different family members.
– Different number of PLD blocks
– Different number of I/O pins
• Many CPLDs have fewer I/O pins than macrocells
– “Buried” Macrocells -- provide needed logic terms
internally but these outputs are not connected externally.
– IC package size dictates # of I/O pins but not the total # of
macrocells.
– Typical CPLD families have devices with differing resources in
the same IC package.

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• High Performance
Features
– 5ns Pin to pin delays on all pins
• Large density range
– 36 to 288 macro cells with 800 to 6400 usable gates
• 5 V in system programmable
– Endurance of 10,000 program/erase cycles.
– Program/erase over full commercial voltage and temperature range.
• Enhanced pin-locking architecture
• Flexible 36V18 function Block.
– 90 product terms drive any 18 macrocells within function block.
– Global and product term clocks, output enables, set and reset signals.
• Slew rate control on individual outputs.
• User programmable ground pin capability
• Advanced CMOS 5V FastFlash technology.
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 Architecture of XC9500
JTAG JTAG In system Programming Controller
port controller

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 Architecture Description
• Each XC9500 device is a subsystem consisting of
multiple
– Function Blocks (FBs)
• Provides programmable logic capability with 36 inputs and 18
outputs.

– I/O Blocks(IOBs)
• The IOBs provide buffering for device inputs and outputs.

– FastConnect switch matrix.

• Connects all FB outputs and inputs signals to the FB inputs.

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Function Block

Global Global
Set/Reset Clocks

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 Function Block
• 18 macrocells per FB ,capable of implementing registered
and combinatorial Logic.

• 36 inputs per FB , 72 true and complement signal into the

programmable AND- array to form 90 product terms.

• Macrocell outputs can go to I/O cells or back into switch

matrix to be routed to this or other FBs.

• Product Term Allocator allocates maximum 90 product terms

to each microcell.

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 Function Block

• The FB also receives global clock, output enable,

and set/reset signals.

• The FB generates 18 outputs that drive the

FastCONNECT switch matrix. These 18 outputs and
their corresponding output enable signals also
drive the IOB.

• Logic within the FB is implemented using a sum-of-

products representation.

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 Function Block

• Thirty-six inputs provide 72 true and complement signals into

the programmable AND-array to form 90 product terms.
• Any number of these product terms, up to the 90 available,
can be allocated to each macrocell by the product term
allocator.
• Each FB (except for the XC9536) supports local feedback
paths that allow any number of FB outputs to drive into its
own programmable AND-array without going outside the FB.
– These paths are used for creating very fast counters and state
machines where all state registers are within the same FB.

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Macrocell

53
 Macrocell
• Five product terms from AND-array are available for use of primary
data inputs.

• The product term allocator associated with each macrocell selects

the five direct terms are used.

• The register can be used as either D or T type F/F and supports both
asynchronous set and reset operations.

• During Power-up,all user register are initialized to the user defined

preload state(default 0)

• All global control signals available to each individual macrocell,

including clock, set/reset,and output enable signal.

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 Macrocell
Set control

Programmable
inversion or XOR
product term

Up to 5 product terms

Global clock or product-term

clock

Reset control

OE control

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Macrocell Clock and Set / Reset Capability

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 Global Control Signals
• In this device architecture there are some dedicated
resources like Global Buffers, that are recommended for
some high fanout nets which,
– Reduce routing congestion.
– Minimizes clock skew.
– Route critical nets.

• Global control signals are:

– Global Set/Reset(GSR)
– Global Clock (GCK)
– Global Tri-state Control (GTS)

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 Clock Buffers
• These are basically used to reduce clock skew.

• These are used to,

– Implement high-speed I/O interfaces.
– Drive high fanout signals such as Clocks,read-write enables
with minimum skew.

• These can also be applied to non-clock signals.

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 GSR Buffers
• These are used to asynchronously SET or RESET F/Fs or
RAM,Memory inside the device.

• Here external reset signal must be connected to GSR

dedicated pin of XC9500.

• GSR can be programmed to either active-high or low.

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 Product Term Allocator
• Controls how the five direct product terms are assigned to
each Macrocell.
• Any Macrocell requiring additional product terms can access
uncommitted product terms in other macrocells within the
FB.

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Product Term Allocator

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 Product Term Allocator
programmable Share terms from above and
steering below
elements

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 FastConnect Switch Matrix
• The FastConnect switch matrix connect signals to the FB inputs.

• All IOB outputs and all FB drive the FastConnect matrix.

• Capable of combining multiple internal connections into a

single Wired-AND output before driving the destination FB.

• This increase the Fan-in without additional time Delay.

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FastConnect Switch Matrix

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 Interconnect structure
XC9500 CPLDs combine a locally efficient logic block with a
globally flexible interconnect structure to provide ideal
connectability for a very large spectrum of designs. The key
qualities of the logic block are:
• 36 input signals presented to the logic block.
• Automatic allocation of product terms as needed within the
function block. The average is 5 product terms per macrocell,
but up to 15 are easily obtained and up to 90 can be used
when needed.
• Formation of efficient counters, multiplexers, shifters, and
parity circuits with an efficiency of one macrocell or less per
bit. The remaining logic is available for use by other functions.
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 Interconnect structure
The key properties of the interconnect structure are:
• Any input pin connects to any function block with constant high
speed across the entire device.
• Any macrocell output can connect to its own or any other
function block with no restriction.
• Macrocells can be internally bused with bit level independent 3-
state control, to form internal data buses with global access to all
logic blocks. (No other CPLD architecture offers this capability,
which saves macrocell logic by using the routing resources to
form multiplexers.)
These key features allow significant design changes to be made
within CPLDs that are already attached to PC boards.
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 I/O Block
• Interfaces between internal Logic and I/O Pins.
• IOB consists of an
– Input Buffer
• Compatible with standard 5V volt CMOS, 5VTTL and 3.3 V signal
levels.
– Output Driver
• Capable of supplying 24 mA output drive.
– Output enable selection multiplexer
• Can be generated from, A product term signal, Any of the global
OE signals
– User programmable ground control
• To reduce system noise generated from large number of
simultaneous switching outputs.

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 I/O Block
• A control Pull-up resistor is attached to each device I/O pin to
prevent them from floating

• The resistor is Active during device programming, System

Power-up and erased device.

• Deactivated in normal operation

• Independent Slew rate control. Output edge rate may be slow

down to reduce noise through programming.

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I/O Block

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 Pin Locking
• The capability to lock the user defined Pin assignments
during design changes depends on the ability of the
architecture to adapt to unexpected changes.

• Small changes, and certainly large ones, can cause the fitter
to pick a different allocation of I/O blocks and pinout.

• Locking too early may make the resulting circuit slower or

not fit at all.

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 Pin Locking
• To address the pin locking issues XC 9500 provides
– Routing resources
• Primary requirement for reliable pin-locking.

– Function Block Fan-in capability

– Product Term Allocation

– Fitter Strategy

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 Technology Used
• CPLD’s are non-volatile devices, I.e retain the program after
Power-off.
• The EPROM, EEPROM, FastFlash are the non-volatile type of
memory.
• The FastFlash technology is used because of its advantage over
the EEPROM.
– High Performance Logic Device.
– High Memory cell density
– Electrical erasable
– 5 V program and erase
– High reliability and endurance
– Process scalability
– Fast device programming times

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 Endurance limits
• The number of times that a cell can be programmed and
erased without any error is called Endurance.

• The devices of XC9500 series have a minimum endurance

limit of 10,000 cycles.

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FIELD PROGRAMMABLE GATE
ARRAY
• A FPGA is a programmable logic device that
supports implementation of relatively large
logic circuits.
• FPGA don't contain AND & OR planes
instead FPGA provide logic blocks for
implementation of the required functions.
• It contains three types of resources:
1. logic blocks
2. I/O blocks
3. Interconnection wires and switches
Figure 3.35. A field-programmable gate array (FPGA).
• Each logic block in an FPGA typically has a smaller
no. of inputs and outputs.
• A variety of FPGA products are on the market,
featuring different types of logic blocks.
• The most commonly used logic block is a LUT,
which contains storage cells that are used to
implement a small logic function.
• Each cell is capable of holding a single logic value.
The storage value is produced as the output of
the storage cell. LUTs of various sizes may be
created, where the size is defined by the no.of
inputs.
• When a ckt is implemented in an FPGA, the logic
blocks are programmed to realize the necessary
functions and the routing channels are
programmed to make the required
interconnection between the logic blocks.
• FPGA are configured by using the ISP method
• The storage cells in the LUTs are volatile
• Often a small memory chip that holds its data
permanently, called PROM , is included on the
circuit board that houses the FPGA
x1

0/1

0/1 x1 x2 f1
f
0/1 0 0 1
0 1 0
0/1
1 0 0
x2 1 1 1

(a) Circuit for a two-input LUT (b) f 1 = x 1 x 2 + x 1 x 2

x1

0
f1
0

1
x2

(c) Storage cell contents in the LUT

A two-input lookup table (LUT).

x1
x2

0/1
0/1
0/1
0/1
f
0/1
0/1
0/1
0/1
x3

A three-input LUT.
 Select

Out
Flip-flop
In1
In2 LUT D Q
In3
Clock

Inclusion of a flip-flop in an FPGA logic block.

PROGRAMMED FPGA
 x3 f

x1

x1 0 x2 0
0 f1 1 f2
0 0
x2 x2 x3
1 0

f1 0
1 f
1
f2
1

Figure 3.39. A section of a programmed FPGA.

• The FPGA has 2 input LUTs and there are 4
wires in each routing channel.
• Fig shows the programmed states of both
the logic blocks and wiring switches in a
section of the FPGA.
• Programmable wiring switches are
indicated by an X
FPGA 4000e Series

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 CLB function generators (F, G, H)
• Use RAM to store a truth table
– F, G: 4 inputs, 16 bits of RAM each(function Generator)
– H: 3 inputs, 8 bits of RAM (function Generator)
– RAM is loaded from an external PROM at system
initialization.
– Each CLB contains two storage elements that can be used to
store the function G.
– So main advantage here is function generator and storage
elements both can be used independently.
– Here each f/f can be triggered either on positive or negative
clock edge due to combination of multiplexer and an inverter.
– Each f/f can be configured to be SET or RESET using (SR).

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Thanks