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Lecture - 04
Structure and Function of Central Processing Unit,
Instruction Cycle
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Processor Organization
Processor Requirements:
 Fetch instruction
 The processor reads an instruction from memory (register, cache, main memory)

 Interpret instruction
 The instruction is decoded to determine what action is required

 Fetch data
 The execution of an instruction may require reading data from memory or an I/O module

 Process data
 The execution of an instruction may require performing some arithmetic or logical operation on data

 Write data
 The results of an execution may require writing data to memory or an I/O module

 In order to do these things the processor needs to store some data temporarily and therefore needs a small
internal memory
CPU With the System Bus
3
CPU Internal Structure 4
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Register Organization
 Within the processor there is a set of registers that function as a level of
memory above main memory and cache in the hierarchy

 The registers in the processor perform two roles:

User-Visible Registers Control and Status Registers

 Enable the machine or assembly  Used by the control unit to control
language programmer to minimize the operation of the processor and
main memory references by by privileged operating system
optimizing use of registers programs to control the execution
of programs
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User-Visible Registers

Categories:
• General purpose
Referenced by means of the • Can be assigned to a variety of functions by the
machine language that the programmer
• Data
processor executes • May be used only to hold data and cannot be
employed in the calculation of an operand address
• Address
• May be somewhat general purpose or may be
devoted to a particular addressing mode
• Examples: segment pointers, index registers,
stack pointer
• Condition codes
• Also referred to as flags
• Bits set by the processor hardware as the result of
operations
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Control and Status Registers

Four registers are essential to instruction execution:

 Program counter (PC)

 Contains the address of an instruction to be fetched

 Instruction register (IR)

 Contains the instruction most recently fetched

 Memory address register (MAR)

 Contains the address of a location in memory

 Memory buffer register (MBR)

 Contains a word of data to be written to memory or the word most recently
read
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Program Status Word (PSW)

Register or set of registers that contain

status information

Common fields or flags include:

• Sign
• Zero
• Carry
• Equal
• Overflow
• Interrupt Enable/Disable
• Supervisor
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Example
Microprocessor
Register Organizations
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Includes the following Instruction

stages:
Cycle

Fetch Execute Interrupt

If interrupts are enabled

Read the next instruction Interpret the opcode and and an interrupt has
from memory into the perform the indicated occurred, save the current
processor operation process state and service
the interrupt
Instruction Cycle
11
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Instruction Cycle State Diagram

Data Flow, Fetch Cycle
13
Data Flow, Indirect Cycle
14
Data Flow, Interrupt Cycle
15
+ Example – Intel 8086 16

(Register Organizations) (1)

• The model includes fourteen 16-bit registers:

• Four segment registers (CS, DS, SS and ES)
• One Instruction pointer
• Four data registers (AX, BX, CX and DX)
• Two pointer registers (BP and SP)
• Two index registers (SI and DI)
• One Status Register (SR), with nine of its bits implemented as status and control
flags
• The 8086 architecture implements independent memory and input/output address
spaces
• The memory address space is 220 = 1,048,576 bytes (1Mbytes) in size and the I/O
address space is 216 = 65,536 bytes (64Kbytes) in size
+ Example – Intel 8086 (Register Organizations) 17

Segment Registers & Memory segmentation

 The 8086 has 1Mbyte address space, but not all is active at one time
 The 1Mbyte of memory is partitioned into segments
 One segment represents an independently addressable memory
locations of 64K consecutive bytes (64Kbytes per segment)
 Each segment is assigned a base address (starting address)
 Only 4 segments are active at one time: code segment, stack segment,
data segment, extra segment
 The segments that are active are identified by the values of four segment
registers:
CS, SS, DS and ES
+ Example – Intel 8086 (Register Organizations) 18

 This gives a maximum of 256Kbytes of active memory:

i. 64Kbytes for program storage (code segment)
ii. 64Kbytes for stack (stack segment)
iii. 128Kbytes for data storage (data and extra segment)
00000H

Code
segment

Stack
segment

CS
SS
Data
DS
segment
ES
Extra
8088/8086
segment

FFFFFH
+ Example – Intel 8086 (Register Organizations) (4) 19

 CS (Code Segment) register

- selects the segment from which instructions of the program are fetched and
executed
 SS (Stack Segment) register
- selects the segment to be used as a stack
 DS (Data Segment) register
- selects the segment in which data are to be processed by the MPU are
stored
 ES (Extra Segment) register
- selects a second 64Kbyte segment for data storage
 The segment registers are user accessible (their value can be changed using
software)
 Therefore, to gain access to another part of memory, simply change the value of
the appropriate registers
+ Example – Intel 8086 (Register Organizations) (5) 20

 Segments can be contiguous (adjacent), disjointed or overlapping

 For e.g., A and B are contiguous, B & C are overlapping, B and D are
disjointed

00000H
A

B
CS
C
SS
D
DS
E
ES
F
G
H

I
J

K
FFFFFH
 Example – Intel 8086 (Register Organizations) 21

 One restriction of the segment base address: only the upper 4 hexadecimal
digit of the address can be changed (these 4 digits are the values inside the
segment registers)

 Examples of valid base addresses are 00000H, 00010H, 00020H etc.

 E.g. Determine the segment base addresses of the code segment, data
segment, extra segment and stack segment if the contents of the segment
registers are as shown below.

CS 0120H

DS 0250H

ES 0500H

SS 2020H
+ Example – Intel 8086 (Register Organizations) (7) 22

Instruction Pointer

 Instruction Pointer (IP) is a 16-bit register that identifies the location of the next
instruction to be fetched from the current code segment (depends on CS)

 It contains the offset of the next instruction instead of its actual address

 IP and CS are both 16-bit registers, but a 20-bit address is needed to access
memory

 The offset in IP is combined with the code segment base address in CS to

generate the address of the next instruction (denoted as CS:IP)

 Every time an instruction is fetched from memory, 8088/8086 updates its IP by

incrementing it by two (to the address of the next instruction)

 To change the active code segment, just load the new value in CS register
+ Example – Intel 8086 (Register Organizations) (8) 23

Data Registers
 8088/8086 has four general purpose data registers:
 A - Accumulator register
 B - Base register
 C - Count register
 D - Data register

 During program execution, they hold the frequently accessed values or results
 All general purpose data registers can be used as the source or destination of
an operand during arithmetic operations (e.g. ADD) or logic operations (e.g.
AND).
 The advantage of storing these data in internal registers instead of memory is
that they can be accessed much faster
+ Example – Intel 8086 (Register Organizations) (9) 24

 Each of these registers can either be accessed as a whole (16 bits) or as two
8-bit registers

 An X after the register letter identifies the reference of a register as a word

(16 bits)

 On the other hand, when referencing one of these registers on 8-bit basis,
the register name is followed by the letter H or L, identifies the high byte or
low byte.
H L
15 87 0
AX
Accumulator
AH AL
BX
Base
BH BL
CX
Count
CH CL
DX
Data
DH DL
+ Example – Intel 8086 (Register Organizations) 25

(10)
Pointer and Index Register
 There are four other general-purpose registers:
i. Two pointer registers
- Base Pointer (BP) and Stack Pointer (SP)
ii. Two index registers
- Source Index (SI) and Destination Index (DI)
 These registers store offset address, which represents the displacement of a storage
location in memory from the segment base address (value in segment registers)
 They are used as pointer or index to select a specific location within a 64Kbyte
segment
 Index registers are used to refer to data in memory relative to data segment or
extra segment
+ Example – Intel 8086 (Register 26

Organizations) (11)

 Pointer registers are used to access memory locations relative to the stack
segment

 The value held inside these registers can be read, loaded or modified
through software

 Unlike data registers, the pointer and index registers can only be accessed
on 16-bit basis
+ Example – Intel 8086 (Register Organizations) 27

(12)
Status Register
 The status register (also called flags register), is a 16-bit
register within 8088/8086
 Only 9 bits of this register are used

X X X X OF DF IF TF SF ZF X AF X PF X CF

Flag register of 8086

+ Example – Intel 8086 (Register Organizations) 28

(13)
 6 status flags: carry flag (CF), parity flag (PF), auxiliary
carry flag (AF), zero flag (ZF), sign flag (SF) and overflow flag (OF)

 The logic state of these flags indicate conditions that are produced as the result of
executing an instruction
 Carry flag (CF): CF is set (1) if there is a carry out or borrow in for the most
significant bit of the result when executing an instruction; otherwise, CF is cleared
(0)
 Parity flag (PF): PF is set (1) if the result produced by an instruction has even
parity (even number of 1); otherwise, PF is cleared (0)
 Auxiliary carry flag (AF): AF is set (1) if there is a carry-out from the low nibble
into the high nibble or a borrow-in from the high nibble into the low nibble of the
lower byte in a 16-bit word; otherwise, AF is cleared (0)
 Zero flag (ZF): ZF is set (1) if the result of an instruction is zero; otherwise, ZF is
cleared (0)
+ Example – Intel 8086 (Register Organizations) 29

(14)

 Sign flag (SF): The MSB of the result is copied into SF. Thus, SF is set (1) is the
result is a negative number or cleared (0) if it is positive.
 Overflow flag (OF): When OF is set, it indicates that the signed result is out of
range. If the result is not out of range, OF remains reset
 E.g. Consider executing the following instructions:

MOV AL, 75
CF = 0 There is no carry out from MSB
ADD AL, 85
PF = 1 The result has even number of 1
1 1 1 1 1 1 AC = 1 There is a carry from bit 3 to bit 4
0 1 0 0 1 0 1 1 7510 ZF = 0 Result is not zero
+ 0 1 0 1 0 1 0 1 8510 SF = 1 Sign bit is 1
1 0 1 0 0 0 0 0 16010 OF = 1 Out of the range (-12810 to 12710)
+ Example – Intel 8086 (Register Organizations) 30

(15)

 Another 3 bits are known as Control Flags: direction flag (DF), interrupt
enable flag (IF) and trap flag

 Trap flag (TF): If TF is set (1), the 8088/8086 goes into single-step mode
of operation (for program debugging)

 Interrupt flag (IF): If IF is set (1), the maskable interrupt is enabled.

Otherwise, the maskable interrupt is disabled

 Direction flag (DF): This flag determines the direction of string operations;
if DF is set (1), string data is transferred from high address to low address;
otherwise, the string data is transferred from low address to high address
+ Summary Structure and Function
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of CPU, Instruction
Cycle
Lecture B - 02
 Processor organization

 Register organization
 User-visible registers
 Control and status registers

 Instruction cycle
 The indirect cycle
 Data flow

 The 8086 processor family

 Register organization
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 Slides adopted from:

 Computer Organization and Architecture, 9th Edition
William Stallings
ISBN-10: 013293633X | ISBN-13: 9780132936330