8085 INSTRUCTIONS

 In order to facilitate efficient programming, 8085

offers 72 different instructions.
 These instructions may be grouped as below
 Data Transfer Group – These instructions transfer (i.e.
copy) the data item from one place (between memory
and registers) to another place.
 Arithmetic Group – This group of instructions are used
to perform a variety of addition or subtraction operation
using ALU.
 8085 INSTRUCTIONS (CONTD.)
 Logical Group – These instructions perform variety of
logical operations such as AND, OR, NOT etc. using ALU.
 Branch and Machine Control Group – This group
includes the instructions that are used for decision
making, changing the execution sequence etc.
 Stack, I/O and Interrupt Control Group – These
instruction are used to manage stack, subroutines, Input-
Output operations, manipulation of various interrupts etc.
 8085 INSTRUCTIONS (CONTD.)
 An instruction is usually organized as below
 Instruction = Opcode + Operand
 Opcode is binary code that is used by the processor to
understand the instruction.
 Operand is the data item upon which processor has to
perform operation, as dictated by the Opcode.
 The Operand can be specified in a number of ways.
 Data Addressing Mode is actually the method by which
an Operand is specified in the instruction.
 There are 246 Opcodes in 8085 due to addressing modes.
 DATA ADDRESSING MODES
An instruction may access data in variety of methods,
called Data Addressing Modes. Following are the
supported addressing modes in 8085.
 Register Addressing.
 Immediate Addressing.
 Direct Addressing.
 Indirect Addressing.
 Implicit Addressing.
 REGISTER ADDRESSING
The designated data item is present in one of the
general purpose register of 8085. This mode is
primarily used to specify variables.
 e.g. MOV C, H
 Copy the content of register H into register C.
 The data item to be copied is present in a CPU
register H.
 Hence, it is Register Addressing Mode.
 Execution of MOV C, H is explained next.
 EXECUTION OF MOV C, H
IR PC Memory
2000
2001 Addr Content
4C
XX ADDRESS : :
: :
MOV C, H
2000 4C
H (4C)
2001 AE
57 DATA
2002 00
2003 76
D
: :
E2 : :
: :
C
CYCLE 1: OPCODE
36
57 FETCH
 MOV RD, RS
MOV RD, RS – Copy the content of Source Register
(RS) into Destination Register (RD).
 RS and RD can be any of the general purpose registers
(A, B, C, D, E, H, L).
 Examples MOV A, D; MOV H, C; MOV A, A etc.
 49 such Opcodes are there for MOV R D, RS.
 This is a 1-byte instruction.
 Takes 1-Machine Cycle (Opcode Fetch) to execute.
 None of the Flags are affected.
 IMMEDIATE ADDRESSING
The designated data item immediately follows the
Opcode and hence the name Immediate Addressing.
This mode is used to specify the constant data.
 e.g. MVI E, ABH
 Copy the 8-bit data ABH into register E.
 The data item (ABH) to be copied is present
immediately after the Opcode MVI E.
 Hence, it is Immediate Addressing Mode.
 Execution of MVI E is explained next.
 EXECUTION OF MVI E, ABH
IR PC Memory

2000
2001
2002 Addr Content
XX
1E ADDRESS : :
: :
2000 MVI E(1E)
1E
2001 AB
DATA
2002 :
2003 :
H L
: :
50 00 : :
: :
E
CYCLE
CYCLE 2:
1: MEMORY
OPCODE 5000 XX
XX
AB FETCH
READ 5001 XX
: :
 MVI R, DATA8
MVI R, DATA8 – Move (i.e. Copy) the 8-bit data
(DATA8) Immediately in to the specified register R.
 R can be any of the 8-bit general purpose registers
(A, B, C, D, E, H, L).
 Examples MVI A, 40; MVI D, 10 etc.
 7 such Opcodes are there for MVI R, DATA8.
 This is a 2-byte instruction.
 Takes 2-Machine Cycles (Opcode Fetch and Memory
Read) to execute.
 None of the Flags are affected.
 LXI RP, DATA16
LXI RP, DATA16 – Load the 16-bit data (DATA16)
Immediately in to the specified register pair RP.
 RP can be one of the register pair (HL, BC, DE, SP).
 RP should be H for HL pair, B for BC Pair, D for DE Pair
 This is a 3-byte instruction.
 Takes 3-Machine Cycles (Opcode Fetch, Memory
Read, Memory Read) to execute.
 None of the Flags are affected.
 Execution of LXI D is explained next.
 EXECUTION OF LXI D, 5000H
IR PC Memory

2003
2000
2001
2002 Addr Content
XX
11 ADDRESS : :
: :
2000 LXI D (11)
11
D E
2001 00
50
XX 00
XX DATA
2002 50
2003 :
: :
: :
: :
CYCLE 3:
2:
1: MEMORY
OPCODE : :
FETCH
READ : :
: :
 DIRECT ADDRESSING
The designated data item is stored in memory and
the memory address is specified directly in the
instruction.
 e.g. LDA 5000H, Load accumulator directly from
memory address 5000H.
 A ← (5000H).
 e.g. STA 5000H, Store accumulator directly at
memory address 5000H.
 A → (5000H).
 Execution of LDA and STA is explained next.
 EXECUTION OF LDA 5000H
IR PC Memory

2003
2000
2001
2002 Addr Content
XX
3A ADDRESS : :
5000 : :
2000 LDA (3A)
3A
W Z
2001 00
50
XX 00
XX DATA
2002 50
2003 :
: :
: :
: :
A
CYCLE 4:
CYCLE 2:
3:
1: MEMORY
4: MEMORY
OPCODE 5000 D8
D8
XX FETCH
READ 5001 :
: :
 EXECUTION OF STA 5000H
IR PC Memory

2003
2000
2001
2002 Addr Content
XX
32 ADDRESS : :
5000 : :
2000 STA (32)
32
W Z
2001 00
50
XX 00
XX DATA
2002 50
2003 :
: :
: :
: :
A
CYCLE 4:
CYCLE 2:
3:
1: MEMORY
4: MEMORY
OPCODE 5000 XX
45
45 FETCH
READ
WRITE 5001 :
: :
 LHLD & SHLD
 LHLD 5000H, Load HL Pair directly from memory
address 5000H.
 L ← (5000H).
 H ← (5001H).
 SHLD 5000H, Store HL Pair directly at memory
address 5000H.
 L → (5000H).
 H → (5001H).
 Execution of LHLD and SHLD is explained next.
 EXECUTION OF LHLD
IR PC Memory

2003
2000
2001
2002 Addr Content
XX
2A ADDRESS : :
5001
5000 : :
2000 LHLD (2A)
2A
W Z
2001 00
50
XX 01
00
XX DATA
2002 50
2003 :
H L
: :
12
XX XX
34 : :
: :
2:
3:
1: MEMORY
CYCLE 4:
5: OPCODE 5000 34
FETCH
READ 5001 12
: :
 EXECUTION OF SHLD
IR PC Memory

2003
2000
2001
2002 Addr Content
XX
22 ADDRESS : :
5001
5000 : :
2000 SHLD (22)
22
W Z
2001 00
50
XX 01
00
XX DATA
2002 50
2003 :
H L
: :
DA FE : :
: :
CYCLE 3:
2:
1: MEMORY
5:
4: OPCODE 5000 FE
XX
FETCH
READ
WRITE 5001 XX
DA
: :
 A Simple Program (P1)
Write an 8085 ALP (Assembly Language Program) to
copy the data 25H at memory location 2100H and
data 30H at memory location 2101H.

MVI A, 25H ; Get 25H in A i.e. A=25H

STA 2100H ; Store A (i.e. 25H) at 2100.
MVI A, 30H ; Get 30H in A i.e. A=30H
STA 2101H ; Store A (i.e. 30H) at 2101.
HLT ; Stop
 Alternate Programs (P1)
MVI L, 25H ; Get 25H in L i.e. L=25H
MVI H, 30H ; Get 30H in H i.e. H=30H
SHLD 2100H ; Store L at 2100 and H at 2101.
HLT

LXI H, 3025H ; Get 25H in L and 30H in H

SHLD 2100H ; Store L at 2100 and H at 2101.
HLT
 A Simple Program (P2)
Two data items are stored at locations 2050H and
2051H. Write an 8085 ALP (Assembly Language
Program) to copy these data at memory locations
2100H and 2101H.

LDA 2050H ; Get data from 2050H in A.

STA 2100H ; Store A at 2100.
LDA 2051H ; Get data from 2051H in A.
STA 2101H ; Store A at 2101.
HLT
 Alternate Program (P2)
LDA SOURCE1 ; Get data from address SOURCE1 in A.
STA TARGET1 ; Store A at address TARGET1.
LDA SOURCE2 ; Get data from address SOURCE2 in A.
STA TARGET2 ; Store A at TARGET2.
HLT ; Stop

 Use of Symbolic address is much preferred in assembly

language.
 At the time of execution any memory address can be
specified as SOURCE and TARGET address.
 A Simple Program (P3)
Two data items are stored at locations 2050H and 2051H.
Write an 8085 ALP (Assembly Language Program) to
exchange data items at these memory locations.

LDA 2050H ; Get DATA1 from 2050H in A.

MOV B, A ; Copy DATA1 in B.
LDA 2051H ; Get DATA2 from 2051H in A.
STA 2050H ; Store DATA2 at 2050H.
MOV A, B ; Get DATA1 in A.
STA 2051H ; Store DATA1 at 2051H.
HLT
 Alternate Program (P3)
LDA ADDR1
MOV B, A ; Get DATA1 into B.
LDA ADDR2 ; Get DATA2 in A.
STA ADDR1 ; Store DATA2 at ADDR1.
MOV A, B ; Get DATA1 in A.
STA ADDR2 ; Store DATA1 at ADDR2.
HLT
 Use of symbolic addresses make the program more
readable and easy to understand.
 INDIRECT ADDRESSING
The designated data item is stored in memory and the
memory address is specified through a register pair (i.e.
indirectly) in the instruction. This addressing mode is
most suitable for tabular processing.
 e.g. MOV B, M
 Copy an 8-bit memory data indirectly into register B, where
memory address is specified by HL Pair.
 B ← ((HL)).
 Since memory address is not the part of instruction it is
indirect addressing.
 Execution of MOV B, M is explained next.
 EXECUTION OF MOV B, M
IR PC Memory

2000
2001 Addr Content
XX
46 ADDRESS : :
5000 : :
MOV B, M
2000 46
(46)
2001 50
DATA
2002 :
2003 :
H L
: :
50 00 : :
: :
B
CYCLE
CYCLE 2:
1: MEMORY
OPCODE 5000 E3
XX
E3 FETCH
READ 5001 XX
: :
 MEMORY MOVES
 MOV R, M
 Copy an 8-bit memory data indirectly into register R.
 R ← ((HL)).
 MOV M, R
 Copy an 8-bit data indirectly into memory from register R.
 R  ((HL)).

 R can be any of the 8-bit general purpose registers (A, B, C, D, E,

H, L).
 14 Opcodes are there for both the MOVes.
 They are 1-byte instructions but take 2-Machine Cycles to execute.
 Execution of MOV M, B is explained next.
 EXECUTION OF MOV M, B
IR PC Memory

2000
2001 Addr Content
XX
70 ADDRESS : :
5000 : :
MOV M, B
2000 70
(70)
2001 50
DATA
2002 :
2003 :
H L
: :
50 00 : :
: :
B
CYCLE
CYCLE 2:
1: MEMORY
OPCODE 5000 XX
3E
3E FETCH
WRITE 5001 XX
: :
 MVI M, DATA8
e.g. MVI M, 50H – Move (i.e. Copy) the 8-bit data
(50H) Immediately in to the memory, specified by
the HL Pair.
 ((HL)) ← 50H .
 This is a 2-byte instruction.
 Takes 3-Machine Cycles (Opcode Fetch, Memory
Read, Memory Write) to execute.
 None of the Flags are affected.
 Execution of MVI M is explained next.
 EXECUTION OF MVI M, 50H
IR PC Memory

2000
2001
2002 Addr Content
XX
36 ADDRESS : :
5000 : :
2000 MVI M(36)
36
2001 50
DATA
2002 :
2003 :
H L
: :
50 00 : :
: :
TMP
CYCLE
CYCLE 2:
1: MEMORY
3: OPCODE 5000 XX
50
XX
50 FETCH
READ
WRITE 5001 XX
: :
 LDAX & STAX
 LDAX RP – Load the accumulator Indirectly through
specified register pair RP.
 A ← ((RP)).
 BC and DE are the only register pairs valid for R P.
 This is a 1-byte instruction but takes 2-Machine
Cycles (Opcode Fetch, Memory Read) to execute.
 STAX RP – Store the accumulator Indirectly through
specified register pair RP.
 Execution of LDAX and STAX is explained next.
 EXECUTION OF LDAX B
IR PC Memory

2001
2000 Addr Content
XX
0A ADDRESS : :
5000 : :
LDAX B
2000 0A
(0A)
2001 :
DATA
2002 :
2003 :
B C
: :
50 00 : :
: :
A
CYCLE
CYCLE 2:
1: MEMORY
OPCODE 5000 45
XX
45 FETCH
READ 5001 :
: :
 EXECUTION OF STAX B
IR PC Memory

2001
2000 Addr Content
XX
02 ADDRESS : :
5000 : :
02
2000 STAX B (02)
2001 :
DATA
2002 :
2003 :
B C
: :
50 00 : :
: :
A
CYCLE 2:
1: MEMORY
OPCODE 5000 XX
45
45 WRITE
FETCH 5001 :
: :
 A Simple Program (P4)
Write an 8085 ALP (Assembly Language Program) to
copy the data 25H at memory location 2100H and data
30H at memory location 2101H using indirect
addressing.
LXI D, 2100H ; Load memory addresses in reg pairs
LXI H, 2101H
MVI A, 25H ; Get 25H in A i.e. A=25H
MVI B, 30H ; Get 30H in B i.e. B=30H
STAX D ; Store A (i.e. 25H) at 2100H indirectly.
MOV M, B ; Store B (i.e. 30H) at 2101H indirectly.
HLT ; Stop
 Alternate Program (P4)
LXI D, ADDR1 ; Load memory addresses in reg pairs
LXI H, ADDR2
MVI A, DATA1 ; Get DATA1 in A (i.e. A=25H)
MVI B, DATA2 ; Get DATA2 in B (i.e. B=30H)
STAX D ; Store A at ADDR1 (2100H)
indirectly.
MOV M, B ; Store B at ADDR2 (2101H)
indirectly.
HLT ; Stop
 Alternate Program (P4)
LXI D, ADDR1 ; Load memory addresses in Reg
pairs.
LXI B, ADDR2
MVI A, DATA1 ; Get DATA1 in A (i.e. A=25H)
STAX D ; Store A at ADDR1 (2100H)
indirectly.
MVI A, DATA2 ; Get DATA2 in A (i.e. A=30H)
STAX B ; Store A at ADDR2 (2101H)
indirectly.
HLT ; Stop
 A Simple Program (P5)
Two data items are stored at locations 2050H and 2051H.
Write an 8085 ALP (Assembly Language Program) to exchange
data items indirectly at these memory locations.

LXI D ADDR1
LXI H ADDR2 ; Load Memory addresses of DATA1 & DATA2.
LDAX D ; Get DATA1 in A.
MOV B, M ; Get DATA2 in B.
MOV M, A ; Store DATA2 at ADDR1.
MOV A, B ; Get DATA1 in A.
STAX D ; Store DATA1 at ADDR2.
HLT
 IMPLICIT ADDRESSING
The designated data item is stored in CPU registers
or machine component but the name of operand is
not defined in the instruction.
 e.g. XCHG, Exchange the content of HL Pair with
DE Pair.
 HL  DE.
 Since operand names HL or DE is not specified in
instruction it is Implicit Addressing.
 Execution of XCHG is explained next.
 EXECUTION OF XCHG
IR PC Memory

2001
2000 Addr Content
XX
EB ADDRESS : :
: :
EB
2000 XCHG (EB)
H L
2001 3A
56
12 78
34 DATA
2002 76
2003 :
: :
: :
: :
D E
CYCLE 1: OPCODE 5000 XX
56
12 78
34 FETCH 5001 XX
: :
 Program (P5) Revisited
Two data items are stored at locations ADDR1 and ADDR2. Write
an 8085 ALP (Assembly Language Program) to exchange data
items indirectly at these memory locations.

LXI D ADDR1
LXI H ADDR2 ; Load Memory addresses of DATA1 & DATA2.
LDAX D ; Get DATA1 in A.
MOV B, M ; Get DATA2 in B.
XCHG ; Exchange the addresses in HL & DE Pair.
HL = ADDR1 and DE = ADDR2.
STAX D ; Store DATA1 at ADDR2.
MOV M, B ; Store DATA2 at ADDR1.
HLT