HOW PROCESSOR WORKS

 Questions to be answered
 How 8085 processor executes the programs.
 How 8085 discriminates between a data and an OPCODE
(Operational code of instruction).

 Instructions to be used
 MOV B, C (Opcode = 41H), Copy the content of
register C into register B.
 MVI A, 41H (Opcode = 3EH), Load data 41H into
register A.
 HOW PROCESSOR WORKS
IR PC Memory
A8 – A15 Addr Content
41
XX 20 00
2001
2000
: :
: :
A0 – A 7 2000 MOV B,C (41)
41
B C LATC 2001 MVI A (3E)
25
62 62 H
2002 41
ALE 2003 :
EN
D0 – D 7 : :
AD0 – AD7 : :
HIGH - : :
A Z
RD 5000 :
20 5001 :
WR : :
 HOW PROCESSOR WORKS
IR PC Memory
A8 – A15 Addr Content
3E
41 20 01
2002
2001
: :
: :
A0 – A 7 2000 MOV B,C (41)
B C LATC 2001 MVI A (3E)
3E
62 62 H
2002 41
ALE 2003 :
EN
D0 – D 7 : :
AD0 – AD7 : :
HIGH - : :
A Z
RD 5000 :
20 5001 :
WR : :
 HOW PROCESSOR WORKS
IR PC Memory
A8 – A15 Addr Content
3E 20 02
2003
2002
: :
: :
A0 – A 7 2000 MOV B,C (41)
B C LATC 2001 MVI A (3E)
62 62 H
2002 41
ALE 2003 :
EN
D0 – D 7 : :
AD0 – AD7 : :
HIGH - : :
A Z
RD 5000 :
41
20 5001 :
WR : :
 HOW PROCESSOR WORKS
 Since PC=2000H, processor knows that whatever stored at
memory location 2000H is OPCODE for an instruction.
 Processor issues 20H (higher byte of address) at A8 – A15
Bus.
 Processor issues 00H (lower byte of address) at AD0 – AD7
Bus.
 After this ALE is made HIGH so lower byte of address
appears at output of latch (marked as A0 – A7).
 After a short duration ALE is made LOW, so lower byte of
address (00H) is locked in latch.
 Now AD bus is free to carry data (marked as D0 – D7).
 HOW PROCESSOR WORKS
 Now processor activates RD’ signal to read the content
of selected memory location (i.e. 2000H).
 Memory delivers 41H (content of location 2000H) to
data bus D0 – D7.
 Processor reads the content of data bus (i.e. 41H) into
IR and increments PC by 1, so PC=2001H.
 After decoding 41H processor understands that it is
MOV B,C.
 Processor copies 62H (Content of register C) into B.
 This completes execution of instruction MOV B,C.
 HOW PROCESSOR WORKS
 Since MOV B,C takes only 1-byte to store in memory
length of this instruction is 1-byte.
 Since MOV B,C is only 1-byte instruction, so it is clear to
processor that next memory location (indicated by
PC=2001H) contains OPCODE for next instruction.
 Now PC supplies the address 2001H to address bus to
read next OPCODE.
 Processor then reads 3EH from location 2001H into IR
and increments PC by 1, so now PC=2002H.
 HOW PROCESSOR WORKS
 After decoding 3EH processor understands it as MVI A
instruction.
 At the same time it also understands that data required
by MVI A is stored at immediate next location i.e. at
2002H, as shown by PC.
 Now processor uses PC=2002H to read 41H from
memory location 2002H.
 But this time 41H is data required by MVI A and is not
the Opcode, so 41H is copied in A and PC is
incremented by 1 i.e. PC=2003H.
 Now processor know that 2003H contains new Opcode.
 HOW PROCESSOR WORKS
 Since MVI A, 41H takes two memory locations, it is a 2-
byte locations which is stored at 2001H & 2002H.
 This clearly means at 2003H a new instruction is stored.
 In this way processor continue to execute instructions
sequentially and is able to discriminate between Opcode
& data.
 MACHINE CYCLES
 Time taken by processor to perform a well defined Read
or Write operation is measured in Machine Cycles.
 When processor reads an Opcode from memory (e.g.
reading 3EH from 2001H), it is called Opcode Fetch
Machine Cycle.
 When processor reads a data required by instruction
from memory (e.g. reading 41H from 2002H), it is called
Memory Read Machine Cycle.
 Similarly if processor has to write a data required by
instruction into memory, it is called Memory Write
Machine Cycle.
 MACHINE CYCLES (CONTD.)
 Time taken by processor to execute an instruction after
fetching the Opcode is called Execution Cycle.
 Time taken by processor to execute an instruction
completely is called Instruction Cycle.
 Instruction Cycle = Fetch Cycle + Execution Cycle
 An Instruction Cycle takes at least one machine cycle
always i.e. Fetch Cycle. E.g. MOV B,C.
 An Instruction Cycle may also take machine cycles after
fetch to finish instruction e.g. MVI A,41H. As discussed it
takes an additional read cycle after fetch.
 MACHINE CYCLES (CONTD.)
 In 8085 an Instruction Cycle may take up to 5 Machine
Cycles including Fetch Cycle.
 To improve understanding of subject it is good to
identify: number of cycles, length of instruction etc. for
each and every instruction.
 More will be discussed on Machine Cycles in later part of
the subject.