VLSI Design

(from fabrication only)

 Module 2- CMOS Fabrication and Layout
VLSI design flow
CMOS process technologies
CMOS Fabrication process
Layout design rules
 VLSI Design Flow
• A Design Flow in VLSI is the sequence of processes/steps
involved in the making of an Integrated Circuit.
• The VLSI design flow can be divided into two parts:
Frontend design flow and Backend design flow. Both
together, allow the creation of a functional chip from
scratch to production.
• Digital VLSI design is often partitioned into five levels
of abstractions: Architecture design,
Microarchitecture design,
Logic design,
Circuit design, and Physical design.
• Specifications comes first, they describe
abstractly the functionality, interface, and the
architecture of the digital IC circuit to be designed.
• Behavioral description is then created to analyze
the design in terms of functionality, performance,
compliance to given standards, and other
specifications.
• RTL description is done using HDLs. This RTL
description is simulated to test functionality.
• From here onwards we need the help of EDA tools,
synthesis tools.
• RTL description is then converted to a gate-level
netlist using logic of the circuit in terms of gates
and connections between them, which are made in
such a way that they meet the timing, power and
area specifications.
• Finally a physical layout is made, which will be
verified and then sent for fabrication.
VLSI Design Flow
Gajaski’s Y-chart :
The Y-chart consists of three major domains,
namely:

1. Behavioral domain

2. Structural domain

3. Geometrical layout domain

• The design flow starts from the algorithm that describes the behavior of
the target chip.
• The corresponding architecture of the processor is first defined.
• It is mapped onto the chip surface by floor planning.
• The next design evolution in the behavioral domain defines finite state
machines (FSMs) which are structurally implemented with functional
modules such as registers and arithmetic logic units (ALUs).
• These modules are then geometrically placed onto the chip surface using
CAD tools for automatic module placement followed by routing, with a
goal of minimizing the interconnects, area and signal delays.
• The third evolution starts with a behavioral module description.
Individual modules are then implemented with leaf cells.

• At this stage the chip is described in terms of logic gates (leaf cells), which can
be placed and interconnected by using a cell placement & routing program.
• The last evolution involves a detailed Boolean description of leaf cells followed
by a transistor level implementation of leaf cells and mask generation.

• In standard-cell based design, leaf cells are already pre- designed and stored in a
library for logic design use.
 Fabrication

• Fabrication plants, or fabs, are enormously expensive to develop and operate.

• Example: fab processing 300 mm wafers in a 45 nm process costs about $3 billion. The
research and development underlying the technology costs another $2.4 billion

• Various semiconductor devices can be constructed by arranging pn junctions in certain

physical structures and combining them with wires and insulators.

• Over the years, silicon semiconductor processing has evolved sophisticated techniques
for building these junctions and other insulating and conducting structures.
 CMOS technologies

• CMOS processing steps can be broadly divided into two parts. Transistors
are formed in the Front-End-of-Line (FEOL) phase, while wires are built in
the Back-End-of-Line (BEOL) phase.
• The steps used through both phases of the manufacturing process are :
1) Wafer Formation 6)Gate Oxide
2) Photolithography 7)Gate and Source/Drain Formations
3) Well and Channel Formation 8) Contacts and Metallization
4) Silicon Dioxide (SiO2) 9) Passivation
5) Isolation 10) Metrology
1) Wafer Formation
• The basic raw material used in CMOS fabs is a wafer or disk of silicon, roughly 75 mm
to 300 mm in diameter and less than 1 mm thick.
• Wafers are thin slices of lightly doped, extremely pure, silicon. Wafers are cut from
boules, cylindrical ingots of single-crystal silicon, that have been pulled from a
crucible of pure molten silicon.

Figure: Silicon Ingot

 Wafer Preparation : Czochralski Method
• It is currently the most common method for producing single-crystal
material.
• Controlled amounts of impurities are added to the melt to provide the
crystal with the required electrical properties.
• A seed crystal is dipped into the melt to initiate
crystal growth. The silicon ingot takes on the
same crystal orientation as the seed.

FIGURE 3.2 Czochralski system for growing Si boules

Adapted from [Schulmann98].)
• A graphite radiator heated by radio-frequency
induction surrounds the quartz crucible and
maintains the temperature a few degrees above the
melting point of silicon (1425 °C).
• The atmosphere is typically helium or argon to
prevent the silicon from oxidizing.
• The seed is gradually withdrawn vertically from the
melt while simultaneously being rotated.
• The molten silicon attaches itself to the seed and
recrystallizes as it is withdrawn.
• The seed withdrawal and rotation rates determine
the diameter of the ingot. Growth rates vary
from 30 to 180 mm/hour.

• Following this method at-least one face is polished

• to a flat, scratch free mirror finish.
2) Photolithography
• The regions of interests ( where we want the materials such as dopants, polysilicon,
metal, and contacts ), are defined using masks. This patterning is achieved by a
process called photolithography, from the Greek photo (light), lithos (stone), and
graphe (picture), which literally means “carving pictures in stone using light.”
• Photolithography is a process where, a pattern is created photographically on a
substrate (silicon wafer)
• The basic principle of photolithography is that using a chemical, called a photo-resist,
which can have it’s chemical properties changed by exposure to light, commonly UV.
• This change in the photo-resist makes it either:
• Resistant to removal by an organic solvent. (Positive photoresist)

• Susceptible to removal by a solvent.(Negative photoresist)

• The wafer is coated with the photoresist and subjected to selective illumination
through the photomask. The photomask is commonly called a reticle
• Photomask is constructed with chromium (chrome) covered quartz glass. The
photomask has chrome where light should be blocked and is usually smaller than the
wafer, e.g.,2 cm on a side.
• A UV light source is used to expose the photoresist.
• The UV light floods the mask from the backside and passes through the clear sections of
the mask to expose the organic photoresist (PR) that has been coated on the wafer.

• A developer solvent is then used to dissolve the soluble unexposed photoresist, leaving
islands of insoluble exposed photoresist. This is termed a negative photoresist.

• A positive resist is initially insoluble, and when exposed to UV becomes soluble. Positive
resists provide for higher resolution than negative resists, but are less sensitive to light.

• As feature sizes become smaller, the photoresist layers have to be made thinner.

• After the initial patterning of photoresist, other barrier layers such as polycrystalline
silicon, silicon dioxide, or silicon nitride can be used as physical masks on the chip.
• A stepper moves the reticle to successive locations to completely expose the wafer.
• Projection printing is normally used, in which lenses between the reticle and wafer
focus the pattern on the wafer surface .
• Older techniques include contact printing, where the mask and wafer are in contact,
and proximity printing, where the mask and wafer are close but not touching.
• The wavelength of the light source influences the minimum feature size that can be
printed.
• Define the minimum pitch : (width + spacing) of a process to be 2b. The resolution of a
lens depends on the wavelength 𝜆 of the light and the numerical aperture NA of the
lens:

• The numerical aperture is : , where n is the refractive index of the

medium (1 for air, 1.33 for water, and up to 1.5 for oil), and 𝛼 is the angle of
acceptance of the lens. Increasing 𝛼 requires larger optics.
• k1 depends on the coherence of the light, antireflective coatings, photoresist
parameters, and resolution enhancement techniques.
• Presently, 0.8 is considered easy, while 0.5 is very hard.

• The depth of focus is:

where k2 ranges from 0.5 to 1.

• Advanced lithography systems with short wavelengths and large numerical apertures
have a very shallow depth of focus, requiring that the surface of the wafer be
maintained extremely flat.
Source Wavelength
1980 Mercury Lamps 365-436nm
0.25 micrometer process generation to Excimer lasers 248(deep ultraviolet)
180nm
Critical layers of 45nm and beyond Argon-fluoride lasers 193nm
• Wavelengths comparable to or greater than the feature size cause distortion in the
patterns exposed on the photoresist.

• Resolution enhancement techniques (RETs) pre-compensate for this distortion so the

desired patterns are obtained .

• These techniques involve modifying the amplitude, phase, or direction of the incoming
light. The ends of a line in a layout receive less light than the center, causing
nonuniform exposure.

• Optical proximity correction (OPC) makes small changes to the patterns on the masks
to compensate for these local distortions.
• The figure shows an example of printing with and without optical proximity

correction. OPC pre-distorts the corners to reduce undesired rounding .

• The cost of masks is also skyrocketing, forcing chip designers to amortize design and
mask expenses across the largest volume possible.
3) Well and Channel Formation: The following are main CMOS technologies:
• n-well process : pMOS transistors fabricated in an n-well and nMOS transistors is
fabricated in the p-type substrate.

• p-well process : The nMOS transistors are built in a p-well and the pMOS transistor
is placed in the n-type substrate
• Twin-well process: In this process, separate optimization of the n-type and p-type
transistors will be provided.

• Triple-well process : The triple-well process has emerged to provide good isolation
between analog and digital blocks in mixed-signal chips.
• Wells and other features require regions of doped silicon. Varying proportions of
donor and acceptor dopants can be achieved using epitaxy, deposition, or
implantation.

• Epitaxy involves growing a single-crystal film on the silicon surface (which is

already a single crystal) by subjecting the silicon wafer surface to an elevated
temperature and a source of dopant material.

• Epitaxy can be used to produce a layer of silicon with fewer defects than the native
wafer surface and also can help prevent latch-up.

• Foundries may provide a choice of epi (with epitaxial layer) or non-epi wafers.
Microprocessor designers usually prefer to use epi wafers for uniformity of device
performance.
• Deposition involves placing dopant material onto the silicon surface and then
driving it into the bulk using a thermal diffusion step. This can be used to build
deep junctions.

• A step called chemical vapor deposition (CVD) can be used for the deposition. CVD
occurs when heated gases react in the vicinity of the wafer and produce a product
that is deposited on the silicon surface. CVD is also used to lay down thin films of
material later in the CMOS process.

• Ion implantation involves bombarding the silicon substrate with highly energized
donor or acceptor atoms. When these atoms impinge on the silicon surface, they
travel below the surface of the silicon, forming regions with varying doping
concentrations.
• At elevated temperature (>800 °C) diffusion occurs between silicon regions
having different densities of impurities, with impurities tending to diffuse
from areas of high concentration to areas of low concentration.

• Therefore, it is important to keep the remaining process steps at as low a

temperature as possible once the doped areas have been put into place.

• However, a high-temperature annealing step is often performed after ion

implantation to redistribute dopants more uniformly. Ion implantation is
the standard well and source/drain implant method used today.
• The first step in most CMOS processes is to define the well regions.

• In a triple-well process, a deep n-well is first driven into the p-type substrate.(high-
energy Mega electron volt levels (MeV) ion implantation is used , typically 2–3 MeV
Implantation can yield a 2.5–3.5 𝜇m deep n-well )
• Such a well has a peak dopant concentration just under the surface and for this reason
is called a retrograde well. This can enhance device performance by providing
improved latch-up characteristics and reduced susceptibility to vertical punch-
through.
• Thick (3.5–5.5𝜇m) resist has to be used to block the high energy implantation where
no well should be formed. Thick resists and deep implants necessarily lead to fairly
coarse feature dimensions for wells, compared to the minimum feature size.
• Shallower n-well and p-well regions are then implanted. After the wells have been
formed, the doping levels can be adjusted (using a threshold implant) to set the desired
threshold voltages for both nMOS and pMOS transistors.
• The nMOS transistor is situated in the p-well located in the deep n-well.
• The pMOS transistors are located in the shallow (normal) n-well.
4) Silicon Dioxide (SiO2) : Various thicknesses of SiO2 is used to make silicon
integrated circuits depending on the particular process. Thin oxides are required for
transistor gates; thicker oxides might be required for higher voltage devices, while
even thicker oxide layers might be required to ensure that transistors are not formed
unintentionally in the silicon beneath polysilicon wires
• Oxidation of silicon is achieved by heating silicon wafers in an oxidizing atmosphere.
• The following are some common approaches:
1) Wet oxidation–when the oxidizing atmosphere contains water vapor. The
Temperature is usually between 900 °C and 1000 °C. This is also called pyrogenic
Oxidation when a 2:1 mixture of hydrogen and oxygen is used.
Wet oxidation is a rapid process.
2) Dry oxidation–when the oxidizing atmosphere is pure oxygen. Temperatures are
in the region of 1200 °C to achieve an acceptable growth rate. Dry oxidation
forms a better quality oxide than wet oxidation. It is used to form thin,
highly controlled gate oxides, while wet oxidation may be used to form
thick field oxides.
3) Atomic layer deposition (ALD)––when a thin chemical layer (material A) is
Attached to a surface and then a chemical (material B) is introduced to
produce a thin layer of the required layer (i.e., SiO2––this can also be used
for other various Dielectrics and metals).
• The process is then repeated and the required layer is built up layer by
layer. The oxidation process normally consumes part of the silicon wafer
• Since SiO2 has approximately twice the volume of silicon, the SiO2 layer
grows almost equally in both vertical directions. Thus, after processing, the
SiO2 projects above and below the original unoxidized silicon surface.
5) Isolation
• Individual devices in a CMOS process need to be isolated from one another so that they
do not have unexpected interactions. In particular, channels should only be inverted
beneath transistor gates over the active area; wires running elsewhere shouldn’t create
parasitic MOS channels.
• Moreover, the source/drain diffusions of unrelated transistors should not interfere
with each other.
• The transistor gate consists of a thin gate oxide layer. Elsewhere, a thicker layer of field
Oxide separates polysilicon and metal wires from the substrate.
• The MOS sandwich formed by the wire, thick oxide, and substrate behaves as an
unwanted parasitic transistor. However, the thick oxide effectively sets a threshold
voltage greater than VDD that prevents the transistor from turning ON during normal
operation.
• The field devices can be used for I/O protection . The source and drain of the transistors

form reverse- biased p–n junctions with the substrate or well, isolating them from
their
neighbours.
• The thick oxide used to be formed by a process called Local Oxidation of Silicon (LOCOS)
A problem with LOCOS-based processes is the transition between thick and thin oxide,
which extended some distance laterally to form a so-called bird’s beak.
• The lateral distance is proportional to the oxide thickness, which limits the packing
density of transistors.
• Starting around the 0.35𝜇m node, shallow trench isolation (STI) was introduced to avoid
the problems with LOCOS. STI forms insulating trenches of SiO2 surrounding the
transistors (everywhere except the active area). The trench width is independent of its
depth, so transistors can be packed as closely as the lithography permits.
• The trenches isolate the wires from the substrate, preventing unwanted channel
Shallow Trench Isolation

1. STI starts with a pad oxide and a silicon nitride layer, which act as the masking layers, as
shown in fig(a).
2. Openings in the pad oxide are then used to etch into the well or substrate region (this
process can also be used for source/drain diffusion).
3. A liner oxide is then grown to cover the exposed silicon (Fig(b)).
• The trenches are filled with SiO2 or other fillers using CVD that does not consume the
underlying silicon (Fig. (c ))
• The pad oxide and nitride are removed and a Chemical Mechanical Polishing (CMP)
step is used to planarize the structure (Fig(d)).
• CMP, as its name suggests, combines a mechanical grinding action in which the
rotating wafer is contacted by a stationary polishing head while an abrasive mixture
is applied.
• The mixture also reacts chemically with the surface to aid in the polishing action. CMP
is used to achieve flat surfaces, which are of central importance in modern processes
with many layers.
• Trench isolation also permits nMOS and pMOS transistors to be placed closer together
because the isolation provides a higher source/drain breakdown voltage–– the voltage
at which a source or drain diode starts to conduct in the reverse-biased condition.
• Deeper trenches increase the breakdown voltage.
6) Gate oxide
• The next step in the process is to form the gate oxide for the transistors which is most
commonly in the form of silicon dioxide (SiO2).

• In the case of STI-defined source/drain regions, the gate oxide is grown on top of the
planarized structure and the oxide structure is called the gate stack.
• The stack term arises because current processes seldom use a pure SiO2 gate oxide,
but prefer to produce a stack that consists of a few atomic layers, each 3–4 A 0 of thick
of SiO2 for reliability, overlaid with a few layers of an oxy-nitrided oxide (one with
nitrogen added).
• The presence of the nitrogen increases the dielectric constant, which decreases the effective
oxide thickness (EOT); this means that for a given oxide thickness, it performs like a thinner
oxide. Being able to use a thicker oxide improves the robustness of the process.
7) Gate and Source/Drain Formations
• When silicon is deposited on SiO2 or other surfaces without crystal orientation, it forms polycrystalline
silicon, commonly called polysilicon or simply poly
• An annealing process is used to control the size of the single crystal domains and to improve the quality of
the polysilicon .
• Undoped polysilicon has high resistivity. The resistance can be reduced by implanting it with dopants
and/or combining it with a refractory metal.
• The polysilicon gate serves as a mask to allow precise alignment of the source and drain on either side of
the gate. This process is called a self-aligned polysilicon gate process.
• Aluminum could not be used because it would melt during formation of the source and drain.
• In earlier processes, early metal-gate processes first diffused source and drain regions, and then formed a
metal gate. If the gate was misaligned, it could fail to cover the entire channel and lead to a transistor that
never turned ON.
• To prevent this, the metal gate had to overhang the source and drain by more than the alignment tolerance
of the process.
• This created large parasitic gate-to-source and gate-to-drain overlap capacitances that degraded switching
speeds.
• The steps to define the gate, source, and drain in a self-aligned polysilicon gate are as
follows:
1) Grow gate oxide wherever transistors are required (area = source + drain + gate)––
elsewhere there will be thick oxide or trench isolation (Figure(a))

2) Deposit polysilicon on chip (Figure (b))

3) Pattern polysilicon (both gates and interconnect) (Figure (c))

4) Etch exposed gate oxide—i.e., the area of gate oxide where transistors are required
that was not covered by polysilicon; at this stage, the chip has windows down to
the well or substrate wherever a source/drain diffusion is required (Figure (d))
5) Implant pMOS and nMOS source/drain regions (Figure (e))

• The source/drain implant density is relatively low, typically in the range 1018–1020 cm–3 of impurity
atom.
• Such a lightly doped drain (LDD) structure reduces the electric field at the drain junction (the junction
with the highest voltage), which improves the immunity of the device to hot electron damage and
suppresses short- channel effects.
• The LDD implants are shallow and lightly doped, so they exhibit low capacitance but high resistance. This
reduces device performance somewhat because of the resistance in series with the transistor.
• Consequently, deeper, more heavily doped source/drain implants are needed in conjunction with the
LDD implants to provide devices that combine hot electron suppression with low source/drain resistance.
A silicon nitride (Si3N4) spacer along the edge of the gate serves as a mask
to define the deeper diffusion regions, as shown in Figure (a)

• A refractory metal is one with a high melting point that will not be
damaged during subsequent processing.
• Tantalum, nickel, molybdenum, titanium, or cobalt are commonly used.
The metal is deposited on the silicon (specifically on the gate polysilicon
and/or source/drain regions).
• A layer of silicide is formed when the two substances react at elevated
temperatures.
• In a polycide process, only the gate polysilicon is silicided. In a silicide process both gate polysilicon and
source/drain regions are silicided. This process lowers the resistance of the polysilicon interconnect
and the source and drain diffusion.
• Figure shows the resultant structure with gate and source/drain regions silicided.

• In addition, SiO2 or an alternative dielectric has been used to cover all areas prior to the next
processing steps.
• CMP step is used to planarize the dielectric, leaving a flat surface for metallization as shown in Figure.
8) Contacts and Metallization
• Contact cuts are made to source, drain, and gate according to the contact mask. These are holes
etched in the dielectric after the source/drain step.
• Older processes commonly use aluminum (Al) for wires, although newer ones offer copper (Cu)
for lower resistance. Tungsten (W) can be used as a plug to fill the contact holes.
• Metallization is the process of building wires to connect the devices. Aluminum can be deposited
either by evaporation or sputtering.
• Evaporation is performed by passing a high electrical current through a thick aluminum wire in
a vacuum chamber. Some of the aluminum atoms are vaporized and deposited on the wafer.
• An improved form of evaporation that suffers less from contamination focuses an electron beam
at a container of aluminum to evaporate the metal.
• Sputtering is achieved by generating a gas plasma by ionizing an inert gas using an RF or DC
electric field. The ions are focused on an aluminum target and the plasma dislodges metal
atoms, which are then deposited on the wafer.
• Wet or dry etching can be used to remove unwanted metal. Piranha solution is a 3:1 to
5:1 mix of sulfuric acid and hydrogen peroxide that is used to clean wafers of organic
and metal contaminants or photoresist after metal patterning.
• Plasma etching is a dry etch process with fluorine or chlorine gas used for metallization
steps. The plasma charges the etch gas ions, which are attracted to the appropriately
charged silicon surface. Very sharp etch profiles can be achieved using plasma etching.
• The result of the contact and metallization patterning steps is shown in Figure
9) Passivation
• The final processing step is to add a protective glass layer called passivation or overglass that prevents
the ingress of contaminants. Openings in the passivation layer, called overglass cuts, allow connection
to I/O pads and test probe points if needed.
• After passivation, further steps can be performed such as bumping, which allows the chip to be directly
Connected to a circuit board using plated solder bumps in the pad openings.
10) Metrology
• Metrology is the science of measuring. Everything that is built in a semiconductor process has to be
measured to give feedback to the manufacturing process.
• This ranges from simple optical measurements of line widths to advanced techniques to measure thin
films and defects such as voids in copper interconnect. A natural requirement exists for in situ real-time
measurements so that the manufacturing process can be controlled in a direct feedback manner.
• Optical microscopes are used to observe large structures and defects
• Scanning electron microscopy (SEM) is used to observe very small features.
• Energy Dispersive Spectroscopy (EDX) bombards a circuit with electrons causing x-ray emission.
• A Transmission Electron Microscope (TEM), which observes the results of passing electrons through a
sample.
 CMOS Fabrication and Layout
• Transistors are fabricated on thin silicon wafers that serve as both a mechanical support
and an electrical common point called the substrate.
• The figure shows a cross-section and corresponding schematic of an inverter. In this
diagram, the inverter is built on a p-type substrate. The pMOS transistor requires an n-
type body region, so an n-well is diffused into the substrate in its vicinity.
• The nMOS transistor has heavily doped n-type source and drain regions and a
polysilicon gate over a thin layer of silicon dioxide (SiO2, also called gate oxide).
n+ and p+ diffusion regions indicate heavily doped n-type and p-type silicon. The
pMOS transistor is a similar structure with p-type source and drain regions.
• The polysilicon gates of the two transistors are tied together somewhere off the page
and form the input A. The source of the nMOS transistor is connected to a metal
ground line and the source of the pMOS transistor is connected to a metal VDD line.
• The drains of the two transistors are connected with metal to form the output Y. A thick
layer of SiO2 called field oxide prevents metal from shorting to other layers except
where contacts are explicitly etched.
• The substrate must be tied to a low potential to avoid forward-biasing the
p-n junction between the p- type substrate and the n+ nMOS source or
drain.
• Likewise, the n-well must be tied to a high potential. This is done by
adding heavily doped substrate and well contacts, or taps, to connect
GND and VDD to the substrate and n-well, respectively.
 Fabrication Process
• The fabrication sequence consists of a series of steps in which layers of the chip are
defined through a process called photolithography.
• Masks specify where the components will be manufactured on the chip.

• The inverter could be defined by a hypothetical set of six masks: n-well, polysilicon,
n+ diffusion, p+ diffusion, contacts, and metal .
Figures below shows cross-sections of the wafer after each processing step :
a) The process of fabrication begins with the bare substrate before processing .

b) Forming the n-well on a bare p-type silicon wafer requires , adding enough Group V dopants into the
silicon substrate to change the substrate from p-type to n-type in the region of the well. To define what
regions receive n-wells, we grow a protective layer of oxide over the entire wafer, then remove it where we
want the wells. The wafer is first oxidized in a high-temperature (typically 900–1200 °C) furnace that
causes Si and O2 to react and become SiO2 on the wafer surface
3) An organic photoresist that softens where exposed to light is spun onto the wafer.

4) The photoresist is exposed through the n-well mask that allows light to pass through
only where the well should be. The softened photoresist is removed to expose the oxide,