Logic circuits

Topic Objectives
❖ Show understanding of Boolean algebra
❖ Show understanding of Karnaugh maps (K-map)
❖ Show understanding of a flip-flop (SR, JK)
❖ Produce truth tables for logic circuits including
half adders and full adders
❖ May include logic gates with more than two inputs
❖ Understand De Morgan’s laws.
❖ Perform Boolean algebra using De Morgan’s laws.
Simplify a logic circuit/expression using Boolean
algebra
Recap: Logic circuit:AS Topic
Recap: Logic circuit AS Topic
Recap: Logic circuit
Recap: Logic circuit
Recap: Logic circuit
 Boolean Algebra basics
• Boolean algebra provide a simplified way of
writing a logic expression and a set of rules
for manipulating an expression
• Understanding of its meaning is important
 Boolean algebra
It is a form of algebra linked to logic circuits
and is based on the two statements:
❖TRUE (1)
❖FALSE (0)
The notation used to represent these two
Boolean operators is:
Boolean Algebra: Rules
Simplification using Boolean algebra
 Simplification using Boolean algebra

Simplify the following

Simplification using Boolean algebra
Simplification using Boolean algebra
Boolean algebra and logic circuits
• One of the advantages of Boolean algebra is
to represent logic circuits in the form of
Boolean Algebra
• It is possible to use the truth table and apply
the sum of products (SoP), or the Boolean
expression can be formed directly from the
logic circuit.
Boolean algebra and logic circuits
 Boolean algebra and logic circuits
Solution
Stage 1: A AND B
Stage 2: B OR C
Stage 3: stage 1 OR stage 2 ⇒ (A AND B) OR (B OR C)
Stage 4: A OR (NOT C)
Stage 5: stage 3 AND stage 4
⇒ ((A AND B) OR (B OR C)) AND (A OR (NOT C))
Written in Boolean algebra form: ((A.B) + (B + C)).(A
+ C)
Boolean algebra and logic circuits
 Boolean algebra and logic circuits
In this example, we will first produce the truth
table and then generate the Boolean expression
from the truth table,
To produce the Boolean expression from the truth table, we only
consider those rows where the output (X) is 1:
 Karnaugh maps (K-maps)
• A Karnaugh map is a method of creating a
Boolean algebra expression from a truth table.
• The Karnaugh map approach is simpler.
• Karnaugh maps were developed to help
simplify logic expressions/circuits.
•
Karnaugh maps (K-maps)
 Rules for construction of K-maps
• The interpretation of a Karnaugh map follows these rules:
– Only cells containing a 1 are considered.
– Groups of cells containing l s are identified where possible,
with a group being a row, a column or a rectangle.
– Groups must contain 2, 4, 8 and so on cells .
– Each group should be as large as possible.
– Groups can overlap.
– If an individual cell cannot be contained in any group it is
treated as being a group.
– Within each group, the only input values retained are those
which retain a constant value throughout the group.
 K-map
• In the column group, B remains unchanged but
A changes so B is retained.
• In the row group, it is A that remains
unchanged.
• The Boolean algebra expression is then just the
sum of these retained values:
– X= A+B
• Thus the Karnaugh map has found the OR
expression without using any algebra .
 Karnaugh maps (K-maps)

Using Karnaugh maps is a much simpler way to do this.

 Worked example
• Let's consider the truth table shown

• The final expression

Worked example
Worked example
Notice the following possible K-map
options:
Notice the following possible K-map
options:
Notice the following possible K-map
options:
 Notice the following possible K-map
options:
The four 1-
values can be
combined at the
four corners;
value B is
constant at 0
and value D is
also constant at
0, giving: B.D
 Further logic circuits
Half adder circuit and full adder circuit
Two important logic circuits used in computers
are
» the half adder circuit
» the full adder circuit.
 The half adder
• A fundamental operation in computing is binary addition.
• The result of adding two bits is either 1 or 0.
• However, when 1 is added to 1 the result is O but there is a carry bit equal
to 1.
• This cannot be ignored if two numbers with several bits in each are being
added.
• The simplest circuit that can be used for binary addition is the half adder.
• The circuit takes two input bits and outputs a sum bit (S) and a carry bit
(C)
 The half adder
• The truth table for the C output is in fact the AND truth table.
• The truth table for the S output can be seen to match that for the XOR
operator
• Therefore, one circuit that would produce the half adder functionality
would contain an AND gate and an XOR gate with each gate receiving
input from A and B.
• Circuit manufacturers prefer to use either NAND or NOR gates.
• The circuit shown in Figure 18.02 consisting only of NAND gates has the
correct logic to produce the C and S outputs and is a likely choice for
implementation .
 Full adder

The sum shows how we have to deal with CARRY from the previous
column.

There are three inputs to consider in this third column, for example, A =
1, B = 0 and C = 1 (S = 0).

This is why we need to join two half adders together to form a full adder:
 The full adder
• At each stage the carry from the previous addition has to be
incorporated into the current addition.
• If a half adder is used each time, there has to be separate
circuitry to handle the carry bit because the half adder only
takes two inputs.
• The full adder is a circuit that has three inputs including the
previous carry bit.
 The full adder
• The truth table is shown as
Full adder
 Full Adder

Discussion
• Can you see how full adders could be combined to handle
addition of, for example, four-bit binary numbers?
• What happens to the carry input for the first addition?
 Full adder
The full adder is the basic building block for
multiple binary additions.
For example, Figure shows how two 4-bit
numbers can be summed using four full adder
circuits.
 sequential circuit
• All of the circuits so far encountered have
been combinational circuits.
• For such a circuit the output is dependent
only on the input values.
• An alternative type of circuit is a sequential
circuit where the output depends on the input
and on the previous output.
 The SR Flip-Flop
• SR flip-flops consist of two cross-coupled NAND gates (note: they can
equally well be produced from NOR gates).
• The two inputs are labelled ‘S’ and ‘R’, and the two outputs are labelled
‘Q’ and ‘Q’ (‘Q is equivalent to NOT Q)

The output from each NOR gate gives a form of positive feedback (known as cross-
coupling, as mentioned earlier
 The SR Flip-Flop
• consider the truth table to match our SR flip-
flop using the initial states of R = 0, S = 1 and
Q = 1.
• The sequence of the stages in the process is
shown
 The SR Flip-Flop
Now consider what happens if we change the
value of S from 1 to 0.
The SR Flip-Flop
 The SR Flip-Flop
• The truth table shows how an input value of S
= 0 and R = 0 causes no change to the two
output values; S = 0 and R = 1 reverses the
two output values
• S = 1 and R = 0 always gives Q = 1 and Q = 0
which is the set value.
 SR Flip Flop
• The truth table shows that SR flip-flops can be
used as a storage/memory device for one bit;
• because a value can be remembered but can
also be changed
• it could be used as a component in a memory
device such as a RAM chip.
• It is important that the fault condition in line
(e) is considered when designing and
developing storage/memory devices.
 The JK Flip-Flop
The SR flip-flop has the following problems:

• » Invalid S, R conditions (leading to

conflicting output values) need to be avoided.
• » If inputs do not arrive at the same time, the
flip-flop can become unstable.

To overcome such problems, the JK flip-flop has

been developed
 The JK flip-flop
• A clock and additional gates are added, which
help to synchronise the two inputs and also
prevent the illegal states shown in line (e) of
Table.
• The addition of the synchronised input gives
four possible input conditions to the JK flip-flop
– »1
– »0
– » no change
– » toggle (which takes care of the invalid S, R states)..
JK flip-flop
JK Flip Flop
» When J = 0 and K = 0, there is no change to the
output value of Q.
» If the values of J or K change, then the value of Q will
be the same as the value of J (Q will be the value of K).
» When J = 1 and K = 1, the Q-value toggles after each
clock pulse, thus preventing illegal states from
occurring (in this case, toggle means the flip flop will
change from the ‘Set’ state to the ‘Reset’ state or the
other way
round).
 JK flip flop
• There is one special case for a NAND gate; when
all inputs are 1 the output is 0.
• If the circuit is in the unset state with Q = 0 and
Q’ =1 this is stable and self consistent as shown
by the following argument:
– the clock and R both input 0
– the top-left NAND gate therefore has output 1
– this then leads to two 1 inputs to the top-right NAND
gate ensuring that Q = 0.
 JK Flip-Flop
If the input from J now becomes 1 and the clock
pulse switches to a 1 then:
• the top-left NAND gate has all 1 inputs
• so the output is 0
• this causes the top-right NAND gate to output
a 1 for Q
• there are now two 1 inputs to the bottom-
right NAND gate
• so the Q’ output becomes 0.
 JK Flip-Flop
• Input K is a clear input.
• JK flip-flop behaves in a similar way to the SR
flip-flop as a storage device for one bit.
• An important difference in that if both J and K
are input as a 1 then the values for Q and Q’
are toggled (they switch value).
• This makes the JK flip-flop a more reliable
device because there is no combination of
input states that leave uncertainty as to
which values are stored
JK Flip-flop