ECE 485/585

Microprocessor System Design

Basic I/O

Yuchen Huang

Maseeh College of Engineering

and Computer Science

Initial content copied verbatim from ECE 485/585 material

developed by Professor Mark G. Faust @ PSU ECE
 Outline
• Simple model of Computation
• Memory Addressing
– Alignment, Byte Order
• 8088/8086 Bus
• Asynchronous I/O Signaling
• Review of Basic I/O
– How is I/O performed
• Dedicated/Isolated /Direct I/O Ports
• Memory Mapped I/O
– How do we tell when I/O device is ready or command complete?
• Polling
• Interrupts
– How do we transfer data?
• Programmed I/O
• DMA
ECE 485/585: Basic I/O 2
 Simplified Model

Control
Memory

Address, Data, Control

Data Path
Keyboard
Microprocessor
Mouse
Video display
[Fetch] Printer
[Decode] Hard disk drive
[Execute] I/O Device Audio card
Ethernet
WiFi
CD R/W
DVD

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 Memory Addressing
• Size of operands
– Bytes, words, long/double words, quadwords
• 16-bit half word (Intel: word) 0x107
• 32-bit word (Intel: doubleword, dword) 0x106
• 64-bit double word (Intel: quadword, qword) 0x105
– Note: names are non-standard 0x104
• SUN Sparc word is 32-bits, double is 64-bits 0x103
• Alignment 0x102
– Can multi-byte operands begin at any (byte) address? 0x101
• Yes: non-aligned 0x100
• No: aligned. Low order address bit(s) will be zero

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 Memory Operand Alignment

0x107
0x106
0x105
0x104
0x103
0x102
0x101
0x100

Aligned Unaligned Aligned Unaligned Aligned Unaligned

word address word address Double word Double word Quad word Quad word
-----0 address address address address
-----00 ----000

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 Memory Operand Alignment
• Why do we care?
• Unaligned memory references
– Can cause multiple memory bus cycles for a single operand
– May also span cache lines
• Requiring multiple evictions, multiple cache line fills
– Complicate memory system and cache controller design

• Some architectures restrict addresses to be aligned

• Even in architectures without alignment restrictions (e.g. Intel x86)
assembler directives are typically used (automatically by compiler) to force
alignment, improving efficiency of generated code.

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 Byte Order: Big Endian or Little Endian

0x107 0x107
0x106 0x106
0x105 0x105
0x104 0x104
0x103 Most significant byte 0x103 Least significant byte
0x102 Least significant byte 0x102 Most significant byte
0x101 0x101
0x100 0x103 0x102 0x100 0x102 0x103
MSB LSB MSB LSB
Little Endian Big Endian

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 Byte Order
• Pros and cons often exaggerated
– Big Endian: Motorola 680x0, Sun Sparc, PDP-11
– Little Endian: VAX, Intel IA32
– Configurable: MIPS, ARM
• Really only matters when
– Communicating between two systems
– Networks and serial interfaces
– Writing debuggers

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ECE 485/585: Basic I/O 9
A Simple Example: Intel 8086/8088
• 16-bit data bus
• 20-bit address (220 = 1M)
• Data/Address Multiplexed
– AD0..AD15 + A16..A19
• 8088 (first PC) had 8 bit
data bus
Minimum/Maximum Mode
Support co-processor
Affects I/O signals

Package Pin Count Constraints

ECE 485/585: Basic I/O 10

8088 Address, Data, Control Signals
How is 8086 different?

D15

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 8088 Timing
• Instruction Cycle
– Fetch/Decode/Execute
– Comprised of one or more Machine Cycles
• Comprised of one or more states

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Block Diagram of 8086-based System

ECE 485/585: Basic I/O 13

Block Diagram of 8086-based System
8086 can access bytes or words
References do not need to be aligned

Address alone is not enough to convey both

location and size of data

BHE# (Bus High Enable)

BHE# A0 Refers to
0 0 16 bits (D0..D15)
0 1 8 bits (D8..D15)
1 0 8 bits (D0..D7)
1 1 <reserved>
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 8086 in Maximum Mode *

*
With 8087 co-processor

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 8086 Bus Timing

Read Cycle

Write Cycle

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 8086 Bus Timing

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 Wait State Generation

18
ECE 485/585: Basic I/O
 8086 Bus Timing

ECE 485/585: Basic I/O 19

 Asynchronous I/O Protocols
Use when sender/receiver may operate at differing speeds
Examples below: level sensitive (not edge triggered)

Source-controlled, no command communication

Suitable for display (e.g. signal to LED, temp value to 7-segment
display) where no issue of lost data

Source-controlled, one-way command communication

Assumes destination is capable of keeping up (e.g. keyboard to
processor). Simple, fast. No validity verification.
t1: allows data to propagate down the bus & settle before arrival of Data Ready (setup time);
t2: the time that DATA READY is high;
t3: After DATA READY is high for t2 time, need t3 to still keep the data valid for the reason of
hold time;
T4: time for sender to reload output data register or for control of device to be re-assigned.

Destination-controlled, one-way command communication

Assumes source is capable of keeping up. Can add Data Error signal
for verification.
t1: is a measure of the propagation delay down the path for the data edge to be seen;
t2: is the amount of time to latch the data;
ECE 485/585: Basic I/O t3: related to hold time. 20
 Asynchronous I/O Protocols
Non-interlocked, request/acknowledge
communication
Suitable for interfacing between devices of different
speeds, helps to ensure both devices ready

Half-interlocked, request/acknowledge
communication
Suitable for interfacing between devices of different speeds,
more reliable

ECE 485/585: Basic I/O 21

 Asynchronous I/O Protocols

Fully-interlocked, request/acknowledge
communication
Suitable for interfacing between devices of different
speeds, more reliable

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Example of Fully Interlock Asynchronous I/O Protocols:
Double Handshake
Sender Receiver
1 I’ve got data for you.
(Asserts /STB)
2 OK. Send it.
(Asserts ACK)
3 (Transmits Data)
Here it is.
(De-asserts /STB)
4 (Receives Data)
3 Got it; awaiting your request to send
1
another byte
(De-asserts ACK)
2 4

3
ECE 485/585: Basic I/O 23
 Port Devices

Microprocessor
Port Peripheral
16
Device
/STB

ACK

ECE 485/585: Basic I/O 24

 8255 PPI Chip
(Programmable Peripheral I/F)
• Provides 3 configurable ports (A,B,C)
– Port A: 8-bit input or output
– Port B: 8-bit input or output
– Port C
• 8-bit input or output
• 2 4-bit ports
• Handshaking signals for ports A, B
• 3 Modes
– Mode 0: No handshake
– Mode 1: Strobe handshake
– Mode 2: Bidirectional handshake
• (Port A only)

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 Addressing the 8255

Why not all address bits used?

Cheap!
“Linear Select Decoding”
Results in “aliased” Port IDs!

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 8255 Control Word Format
• MSB (D7) Controls
– Mode Control Word
– Bit Set/Reset
• Set/clear bits in Port C
• In Mode 1/2

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 I/O Issues
• What instructions does the processor use to communicate with I/O
devices? Example: disk read: address, number of bytes, “read”
– Isolated (Direct) I/O
– Memory mapped I/O
• How do we know if an I/O device is ready or an I/O operation is
complete
– Polling
– Interrupts
• How do we transfer data between the I/O device and memory?
– Programmed I/O (PIO)
– Direct memory access (DMA)
• Bus Mastering

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 Isolated (Direct) I/O
• I/O Address Space Separate from Memory Address Space
• I/O “Ports” (Numbered)
• Dedicated I/O Instructions
– IN <destination>, <port> ; fixed or variable port
– OUT <port>, <source> ; fixed or variable port
• Pros
– Very easy to interface peripherals
– Port Device ICs (e.g. 8255)
• Cons
– Additional H/W and instructions required
– May not be as flexible as memory-mapped I/O
• Depending upon addressing modes implemented for IN, OUT

ECE 485/585: Basic I/O 29

 Simple 8255 Example

Configure Port A as input, B as output

Configure both halves of Port C as output
Input data from Port A
Output it to Port B and Port C

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 I/O Port Addresses

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 Memory-Mapped I/O
• I/O Treated Exactly Like Memory Access
• I/O Devices Share Address Space with Memory
• Use Normal Instructions for I/O
– MOV AL, MemAddr ; read byte
– MOV MemAddr, AL ; write byte
– Full addressing modes available (++, [])
– Caution: I/O registers read as side-effect
• I/O Devices Do Address Decoding

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 Memory-Mapped I/O
• Pros
– “Regular” architecture
– No special I/O instructions
• Simplifies processor architecture
• Can write I/O device drivers in C
– Full addressing modes available
• Increment, indirect
• Memory to memory instructions
– Can test/set bits in a control word without using an additional I/O instruction to bring the
control word into a register
– Can protect against random process accessing I/O by using page
tables (don’t map I/O addresses into process address space)
• Cons
– Must have solution to avoid caching device registers!
– Address space consumed (not really an issue!)
• What does Intel IA32 architecture use?
Both!
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 How Do You Get Notified of I/O
Completion/Ready?
• Polled I/O
• Interrupt Driven I/O

ECE 485/585: Basic I/O 34

 Polling
READB: IN AL, BUSY ; get
BUSY flag
TEST AL, BUSY_BIT ; test BUSY bit
JNE READB ; still busy -- loop
IN AL, DATAP ; read data
Simplified Polling Code Fragment

Memory

Address, Data, Control

Microprocessor

I/O Device

ECE 485/585: Basic I/O 35

 Interrupt-Driven I/O
• Permits the processor to execute useful instructions instead
of polling an I/O device
• The I/O device interrupts the processor when it needs
attention (e.g. has data) or an I/O operation has completed
– Keyboard character typed
– Earlier requested disk block has been read

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 Interrupt Processing Sequence
• Interrupt occurs
• Push current processor state onto stack
– Flags
– CS:IP
• Clear IF and TF (Interrupt and Trap Flags)
– Prevents further interrupts
• Retrieve Instruction Pointer (CS:IP) Using Interrupt Vector as
index into Interrupt Descriptor Table (IDT)
• Begin executing with new CS:IP of ISR
• Service the interrupt (Interrupt Service Routine)
• ISR ends by executing IRET instruction (explicit)
– Pops CS:IP and Flags from Stack

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 START: MOV AX, CX ; 1
comment Interrupt occurs
MOV CX, ICOUNT
; comment
.
2
Push Flags and CS:IP (PC) onto stack
. Clear IF and TF (interrupt/trap flag)
.
Executing Code Stack
.
CS:IP
ISR: PUSH AX Flags
; comment
PUSH BX 4
IN … IRET pops stack and execution resumes
where interrupted
IRET
Interrupt Service Routine
Entry number, not address
255

3
Interrupt Descriptor Table IDT[Vector x 4] to get new CS:IP

1
0 CS:IP (PC) of ISRs
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Why multiply interrupt by 4?

ECE 485/585: Basic I/O 39

 Interrupt Hardware: Vectors
NMI Non-maskable Interrupt
INTR Interrupt
INTA# Interrupt Acknowledge
AD0-
AD15 Type vector

Intel
8086

ECE 485/585: Basic I/O 40

 The Interrupt Mechanism

• Hardware Interrupts (Asynchronous)

– Non-Maskable Interrupts (NMI)
– Priority Maskable Interrupts (INTR)
• Software Interrupts (Synchronous)
– Nomenclature varies
• Intel calls these “exceptions” to distinguish them from
H/W “interrupts”
• Often called “traps” or “faults”

ECE 485/585: Basic I/O 41

 The Interrupt Mechanism
• Non-Maskable Interrupts
– Power Failure
• Enough time to save state and shutdown gracefully
• Priority Maskable Interrupts
– I/O Devices Assigned Different Priorities
• Relative importance of servicing request
– (e.g. keyboard or disk)
• Ability of device to buffer data

ECE 485/585: Basic I/O 42

 The Interrupt Mechanism

• Software Interrupts (Synchronous)

– Divide-by-Zero
– Page fault or segmentation violation
– Debugging (breakpoints and single step)
– Operating System Calls
• User program makes O.S. request
• INT ## instruction

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ECE 485/585: Basic I/O 44
 How Do You Transfer Data?
• Programmed I/O
• DMA (Direct Memory Access)

ECE 485/585: Basic I/O 45

 Programmed I/O: Input Example

Memory

Address, Data, Control

Microprocessor

I/O Device

Requires fetching of instructions to be executed to do the I/O

Requires moving data from I/O device to processor and then to memory
ECE 485/585: Basic I/O 46
 Disk Read Example
• Initiate an I/O operation (e.g. read a block of 512 bytes from disk)
– Write to device indicating: operation (read), disk address, bytes, etc
– Write to device instructing it to begin
• Determine when device has completed operation and has data
– Polling
– Read the device’s status
– Interrupt
– Receive interrupt when I/O device operation complete and data ready
• Transfer data from device to memory
– Programmed I/O (read a byte at a time from I/O device to processor then to memory)
– DMA
– Rely on hardware to transfer the data without involving the CPU

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 Programmed I/O
Read Count Bytes

START: MOV BX, OFFSET BUFFER

MOV DX, FFF8H ; set up I/O port
MOV CX, COUNT ; set up byte
count 8
READB: IN AL, DX ; read byte 9+9
MOV [BX], AL ; copy to buffer 3
INC BX ; increment 5/17 if loop taken
pointer 34-46
LOOP READB ; decrement/test
CX Simplified I/O Read Code Fragment

How many clock cycles?

ECE 485/585: Basic I/O 48

 START: MOV BX, OFFSET BUFFER

count
Programmed I/O
MOV
MOV
DX, FFF8H
CX, COUNT
; set up I/O port
; set up byte

READB: IN AL, DX ; read byte

MOV [BX], AL ; copy to buffer
INC BX ; increment
pointer
Simplified
LOOP READBI/O Read Code Fragment
; decrement/test
CX

Memory

Microprocessor Address, Data, Control

I/O Device

ECE 485/585: Basic I/O 49

 Direct Memory Access (DMA)

Memory

Address, Data, Control

Microprocessor

I/O Device

DMA Controller

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 DMA (Detail)
mP “floats” its bus interface pins

AEN

5
5

3
1
4
ECE 485/585: Basic I/O 51
 DMA Timing

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 8237 DMA Controller

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 8086 Bus Timing

ECE 485/585: Basic I/O 54

 Summary
– Architecture
• Dedicated (Isolated or Direct) I/O Ports
• Memory-Mapped I/O
– Event Notification/Synchronization
• Polling
• Interrupt-Driven
– Data Transfer Programming
• Programmed I/O
• Direct Memory Access (DMA)

ECE 485/585: Basic I/O 55

System Bus/Global Bus
Local Bus

Block Diagram of IBM PC Motherboard

ECE 485/585: Basic I/O 56

 Technical Specifications for Intel
Microprocessors

ECE 485/585: Basic I/O 57

ECE 485/585: Basic I/O
Binary compatibility from 1978 to 2010!! 58