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UNIT NO 2

ARITHMETIC FOR COMPUTERS

2.1 Addition and Subtraction

II IV

CS 8491
Computer Architecture
(Common to CSE & IT)
 CS 8491
COMPUTER ARCHITECTURE (Common to CSE & IT )

2.1 MIPS Addition and Subtraction

• All arithmetic and logic operations take place in registers.

• We have both formats for addition and subtraction.
• All addition and subtraction instructions have three
operands;
• the first holds the sum or difference, and the second and
third hold the values being added or subtracted.
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COMPUTER ARCHITECTURE (Common to CSE & IT )

Addition

The add instruction adds two registers and places the result
in another register. The format is

add Rd, Rs, Rt # Rd = Rs + Rt

The value that was in Rd before the add is replaced with the
sum Rs + Rt. Rs and Rt are unchanged. For example:

add $t3, $t1, $t2 # $t3 = $t1 + $t2

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addi - Add Immediate

The addi instruction adds a register and an immediate value (a

constant) and places the result in a register. The format is

addi Rd, Rs, immed # Rd = Rs + immed

The value that was in Rd before the add is replaced with the
sum Rs + immed. Rs is unchanged. For example:

addi $t2, $t1, 10 # $t2 = $t1 + 10

addi $t1, $t1, 1 # $t1 = $t1 + 1 ($t1++)
addi $t2, $t1, -5 # $t2 = $t1 - 5
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COMPUTER ARCHITECTURE (Common to CSE & IT )

Subtraction
The sub instruction subtracts two registers and places the result in
another register. The format is:

sub Rd, Rs, Rt # Rd = Rs - Rt

The value that was in Rd before the sub is replaced with the difference
Rs - Rt. Rs and Rt are unchanged. For example:

sub $t3, $t1, $t2 # $t3 = $t1 - $t2

The value that was in $t3 before the sub is replaced with the difference
$t1 - $t2. $t1 and $t2 are unchanged. Note that there is no subi
instruction; to subtract a constant, use addi with a negative constant.
 CS 8491
COMPUTER ARCHITECTURE (Common to CSE & IT )

Boolean Addition
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COMPUTER ARCHITECTURE (Common to CSE & IT )

Boolean Subtraction
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Half-Adder:
•A half-adder is a combinational circuit that can be used to add two binary bits.

• It has two inputs that represent the two bits to be added and two outputs, with one producing the
SUM output and the other producing the CARRY.

Block schematic of half-adder

Truth table of a half-adder

Inputs Outputs
A B Carry (C) Sum (S)

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
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K-map simplification for carry and sum:

Boolean expression for SUM and CARRY

Sum, S = A’B+ AB’= AÅB

Carry, C = A . B
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Logic diagram of the half adder

Logic Implementation of Half-adder

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Full-Adder:

•A full adder is a combinational circuit that forms the arithmetic sum of

three input bits. It consists of 3 inputs and 2 outputs.

•Two of the input variables, represent the significant bits to be added.

• The third input represents the carry from previous lower significant
position. The block diagram of full adder is given by,
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Truth Table:
Inputs Outputs

A B Cin Sum (S) Carry (Cout)

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1
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From truth table, the Karnaugh map

,
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The Boolean expressions for the SUM and CARRY outputs are given by the equations,

Sum, S = A’B’Cin+ A’BC’in + AB’C’in + ABCin

Carry, Cout = AB+ ACin + BCin .

Logic diagram for the above functions

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• The logic diagram of the full adder can also be implemented with two half- adders and one OR

gate.

• The S output from the second half adder is the exclusive-OR of Cin and the output of the first
half-adder, giving

Sum = Cin Å (A Å B)
[xÅy = x‘y+ xy‘]
= Cin Å (A‘B+AB‘)

= C‘in (A‘B+AB‘) + Cin (A‘B+AB‘)‘

[(x‘y+xy‘)‘= (xy+x‘y‘)]
= C‘in (A‘B+AB‘) + Cin (AB+A‘B‘)

= A‘BC‘in + AB‘C‘in + ABCin + A‘B‘Cin .

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carry output is,

Carry, Cout = AB+ Cin (A’B+AB’)

= AB+ A‘BCin+ AB‘Cin

= AB (Cin+1) + A‘BCin+ AB‘Cin

[Cin+1= 1]
= ABCin+ AB+ A‘BCin+ AB‘Cin

= AB+ ACin (B+B‘) + A‘Bcin

= AB+ ACin+ A‘Bcin

= AB (Cin+1) + ACin+ A‘Bcin

[Cin+1= 1]
= ABCin+ AB+ ACin+ A‘Bcin

= AB+ ACin+ BCin (A +A‘)

= AB+ ACin+ BCin.

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Implementation of full adder with two half-adders and an OR gate

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Binary Adder (Parallel Adder):

• The 4-bit binary adder using full adder circuits is capable of adding two 4-bit

numbers resulting in a 4-bit sum and a carry output as shown in figure

below.

4-bit binary parallel Adder

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The 4-bit words to be added be represented by, A3A2A1A0= 1111 and B3B2B1B0= 0011.
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• The bits are added with full adders, starting from the least significant position, to form the
sum it and carry bit.

• The input carry C0 in the least significant position must be 0.

• The carry output of the lower order stage is connected to the carry input of the
next higher order stage. Hence this type of adder is called ripple-carry adder.

• In the least significant stage, A0, B0 and C0 (which is 0) are added resulting in sum S0 and
carry C1.

• This carry C1 becomes the carry input to the second stage.

• Similarly in the second stage, A1, B1 and C1 are added resulting in sum S1 and carry C2, in

the third stage, A2, B2 and C2 are added resulting in sum S2 and carry C3, in the third stage,

A3, B3 and C3 are added resulting in sum S3 and C4, which is the output carry.

• Thus the circuit results in a sum (S3S2S1S0) and a carry output (Cout).
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Carry Propagation–Look-Ahead Carry Generator:

• In Parallel adder, all the bits of the augend and the addend are available for computation at
the same time
.
• The carry output of each full-adder stage is connected to the carry input of the next high-
order
stage.

• Since each bit of the sum output depends on the value of the input carry, time delay occurs in
the addition process. This time delay is called as carry propagation delay.

4-bit Parallel Adder

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Full-Adder circuit

Carry generate, Gi = Ai Åbi

Carry propagate, Pi = Ai Å Bi

Output sum and carry can be expressed as,

Si = Pi Å Ci Ci+1 = Gi Å PiCi
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•Gi (carry generate), it produces a carry 1 when both Ai and Bi are 1, regardless of the input carry
Ci

•Pi (carry propagate) because it is the term associated with the propagation of the carry from Ci to
Ci+1.

•The Boolean functions for the carry outputs of each stage and substitute for each Ci its value from

the previous equation:

•C0= input carry

C1= G0 + P0C0

C2= G1 + P1C1 = G1 + P1 (G0 + P0C0)

= G1 + P1G0 + P1P0C0

C3= G2 + P2C2 = G2 + P2 (G1 + P1G0 + P1P0C0)

= G2 + P2G1 + P2P1G0 + P2P1P0C0

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Logic diagram of Carry Look-ahead Generator

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4-Bit Adder with Carry Look-ahead

 CS 8491
COMPUTER ARCHITECTURE (Common to CSE & IT )

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