Scribd
Upload
22 views19 pages

Design of Memory Elements

Memory Element Designing

Uploaded by

nmdrafiqj2003
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
22 views19 pages

Design of Memory Elements

Memory Element Designing

Uploaded by

nmdrafiqj2003
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 19

Design of memory elements

Memory Basics
DRAM
Realization of DRAM
• 1 Transistor (1T) DRAM cell
• 3 Transistor (3T) DRAM cell
• 4 Transistor (4T) DRAM cell
1T DRAM cell
1T DRAM cell

• Accessed using single NMOS


• Storage is achieved by capacitor
(Vdd or Ground)
• Control Input, word line, WL
• Data I/O : Bit Line

WL BL M1 Cs
1 Vdd ON Charged to Vdd-Vth

0 Vdd OFF Data gets stored on


the capacitor (Hold
Operation)
DRAM Operation
Refresh Rate

• The read-out of the 1T DRAM cell is destructive; read and refresh


operations are necessary for correct operation.
• Unlike 3T cell, 1T cell requires presence of an extra capacitance that
must be explicitly included in the design.
• When writing a “1” into a DRAM cell, a threshold voltage is lost. This
charge loss can be circumvented by bootstrapping the word lines to a
higher value than VDD
3T DRAM Cell

• Reads are non-destructive


• Value stored at node X when writing a “1” = VWWL-Vtn
• BL1 and BL 2 is initially at Vdd
• BL1 is used to perform write and BL 2 is used for read operation
3T DRAM Operation ( Always reads the inverted value)

To Write Logic 1

Operation Data WWL RWL BL1 BL2 M1 X M2 M3


(WS) (RS)

Precharge 1 0 0 Vdd Vdd - - - -


(PC=1)
Write 1 1 0 Vdd Vdd ON Vdd-Vtn ON (Data gets stored on the gate of M2 OFF
Refresh 1 0 0 Vdd Vdd OFF Vdd-Vtn ON (Data gets stored on the gate of M2 OFF
(Hold)
Read 1 0 1 Vdd 0 OFF Vdd-Vtn ON ON
3T DRAM Operation ( Always reads the inverted value)

To Write Logic 0

Operation Data WWL RWL BL1 BL2 M1 X M2 M3


(WS) (RS)

Precharge 1 0 0 Vdd Vdd - - - -


(PC=1)
Write 0 1 0 0 Vdd ON 0 OFF (0 gets stored on the gate of M2) OFF
Refresh 1 0 0 0 Vdd OFF 0 OFF (0 gets stored on the gate of M2) OFF
(Hold)
Read 1 0 1 0 Vdd OFF 0 OFF (0 gets stored on the gate of M2) ON
4T – DRAM Cell – Write Operation

M1 M2 BL BL’ RS CS I/O I/O’ M3 M4 M5 M6 M7 M8


Precharge ON ON Vdd Vdd 0 0 1 0 OFF OFF OFF OFF OFF OFF

Write ON ON 1 0 0 1 1 0 ON ON OFF OFF OFF OFF


Write ON ON 1 0 1 0 1 0 OFF OFF ON ON OFF(0) ON(1)
4T – DRAM Cell – Read Operation

M1 M2 BL BL’ RS CS I/O I/O’ M3 M4 M5 M6 M7 M8


Precharge ON ON Vdd Vdd 0 0 - - OFF OFF OFF OFF OFF(0) ON(1)

Read ON ON 1 0 1 0 - - OFF OFF ON ON OFF(0) ON(1)


Read ON ON 1 0 0 1 1 0 ON ON OFF OFF OFF(0) ON(1)
Realization of SRAM Cell
• Capable of retaining the data as long as the power is applied.
• Does not require any periodic refreshing.
6T SRAM Cell

M1 M2 BL BL’ RS CS I/O I/O’ M3 M4 M5 M6 Inv1 Inv2


Precharge ON ON Vdd Vdd 0 0 1 0 OFF OFF OFF OFF - -

Write ON ON 1 0 0 1 1 0 ON ON OFF OFF - -


Write ON ON 1 0 1 0 1 0 OFF OFF ON ON 0 1

M1 M2 BL BL’ RS CS I/O I/O’ M3 M4 M5 M6 Inv1 Inv2


Precharge ON ON Vdd Vdd 0 0 - - OFF OFF OFF OFF 0 1

Read ON ON 1 0 1 0 - - OFF OFF ON ON 0 1


Read ON ON 1 0 0 1 1 0 ON ON OFF OFF 0 1
Dynamic CMOS Logic - Monotonicity
Dynamic CMOS – Charge Sharing -
Redistribution
Charge Sharing – Solutions :-
1. Static Bleeder
2. Precharge of Internal Nodes

You might also like