Tessent: Scan and ATPG

Module 4

Understanding ATPG
Messaging
 Objectives

Upon completion of this module, you will be able to:

 Read and analyze messages at invocation.

 Analyze and explain DRC messaging.
 Analyze ATPG reporting.
 Explain how to use test coverage reporting.
 Use common methodologies to attain a quick estimate of test
coverage.

4-2 • Tessent: Scan and ATPG: Understanding ATPG Messaging Copyright © 1999-2009 Mentor Graphics Corporation
 Messages at Invocation
 Example of a Tessent FastScan message at invocation:
fastscan module4_1.v -verilog -lib ../../libraries_1_to_4/adk.atpg -dofile fs.do -log mgc.log
-replace -nogui -load_warnings
// Tessent FastScan v8.XXXX_X.XX Mon Nov XX XX:XX:XX PST 2XXX Current version
// Copyright Mentor Graphics Corporation 2XXX of Tessent FastScan
//
// All Rights Reserved.
//
// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH
// IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS
// SUBJECT TO LICENSE TERMS.
//
// Mentor Graphics software executing under x86 Linux.
// 32 bit version
// Host: System1 (2 x 2.6 GHz, 15739 MB RAM, 51199 MB Swap)
//
// Compiling library ...
// Reading DFT Library file ../../libraries_1_to_4/adk.atpg Compiles DFT
// Finished reading file ../../libraries_1_to_4/adk.atpg library then
// Reading Verilog Netlist ... parses netlist
// Reading Verilog file module4_1.v
// Finished reading file module4_1.v Warns about
undriven nets
// Warning: Net 'CO' in module 'picalu_DW01_sub_9_0' is not driven
// Warning: Net 'CO' in module 'picalu_DW01_add_9_0' is not driven (-load_warnings
provides detail)
Sample.log
4-3 • Tessent: Scan and ATPG: Understanding ATPG Messaging Copyright © 1999-2009 Mentor Graphics Corporation
 Messages at Invocation: Warnings
 Tessent FastScan or Tessent
TestKompress reports the following types
of warnings at invocation:

// Copyright (c) Mentor Graphics Corporation, XXXX, All Rights Reserved.

// UNPUBLISHED, LICENSED SOFTWARE.

// CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE Major problems at invocation cause the
// PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS. tool to error and exit.
//
// USE OF THIS SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS.
//
//
// Mentor Graphics software executing under Sun SPARCOS.
// 32 bit version
//
// Compiling library …
... If a model is defined multiple times
// Warning: Model name 'EN0_UDP' is duplicated; Last model definition is selected in the DFT library, the last defined
...
// Warning: 1 case: Undefined module pin assumed to be output (model) is used.
// Warning: 5 cases: Undriven net in netlist module
// Warning: 3 cases: Undefined module pin assumed to be input Warning summary of unused nets,
// Note: Invoke with ‘-load_warnings’ to see detailed library and netlist warnings
// Reading Verilog Netlist ...
...
undefined module pins.
// Warning: Floating input 'fr_ct_sel' at instance 'design_core0' in module 'design'
...
Warns of unused and floating nets.
// Warning: Net 'Q0' in module 'R64X8S' is not driven

Sample_2.log

4-4 • Tessent: Scan and ATPG: Understanding ATPG Messaging Copyright © 1999-2009 Mentor Graphics Corporation
 DRC Messaging
The tools replace the design cells in the netlist
with DFT primitives during flattening.
// Warning: Rule FN1 violation occurs 1463 times Stores netlist in an internal
// Warning: Rule FN2 violation occurs 31 times format (flattened) and a
// Flattening process completed, design_cells=136106 leaf_cells=5980 library_primitives=381930 summary is reported
netlist_primitive=8 sim_gates=358763 PIs=140 POs=142 CPU time=10.58 sec.
// ---------------------------------------------------------------------------
// Begin circuit learning analyses. Classifies design
// --------------------------------------------------------------------------- characteristics to improve
// Equivalent gates=8783 classes=3787 CPU time=2.64 sec. ATPG efficiency
// Learned gate functions: #BUFs=432 #INVs=123 #XORs=4843 #MUXs=13340
// Learned relationships: #EQ_MUXs=24 #EQ_BUSs=2
// Learned tied gates: #TIED_XORs=51 #TIED_ANDs=50 #TIED_ORs=15
// Learning activity limit exceeded: static learning process was truncated.
// Learning completed, implications=202349, tied_gates=65880, CPU time=0.87 sec. Verifies scan chain
// --------------------------------------------------------------------------- operation through
// Begin scan chain identification process, memory elements = 11622. simulation using the
// ---------------------------------------------------------------------------
// Reading group test procedure file testproc. .testproc file
// Bus gates have connectivity to clocks.
// Simulating load/unload procedure in group1 test procedure file.
// Tracing main shift ...
// Chain = chain1 successfully traced with scan_cells = 248.
// Tracing independent shift ...
// Chain = chain1 successfully traced with scan_cells = 248.
// Warning: Traced number shifts (248) doesn't match entered value (260). (T18-1)
// 248 scan cells have been identified in 1 scan chain. Sample_3.log
// Warning: 66 edge-triggered clock ports set to stable high. (D7)

Example of DRC messaging

4-5 • Tessent: Scan and ATPG: Understanding ATPG Messaging Copyright © 1999-2009 Mentor Graphics Corporation
 DRC Messaging (Cont.)
The tool identifies nonscan logic behavior and
performs clock rule checks.
// ---------------------------------------------------------------------------
// Begin transparent latch checking for 133 latches. Identify transparent latches
// ---------------------------------------------------------------------------
// Warning: 119 latches not transparent due to uncontrollable. (D6)
// Number transparent latches = 14.
// ---------------------------------------------------------------------------
// Begin scan clock rules checking.
Perform clock rule checking
// ---------------------------------------------------------------------------
// All scan clocks successfully passed off-state check.
// 1978 sequential cells passed clock stability checking.
// All scan clocks successfully passed capture ability check.
// Warning: There were 11 clock rule C3 fails (clock may capture data affected by its captured data).
// Warning: There were 186 clock rule C7 fails (scan cell capture ability check).
// Warning: Trailing edge triggered device can capture data affected by leading edge.
// ---------------------------------------------------------------------------
// 11122 non-scan memory elements are identified. Identify non-scan memory
// --------------------------------------------------------------------------- elements and classify
// 520 non-scan memory elements are identified as TIE-0. (D5)
// 236 non-scan memory elements are identified as TIE-1. (D5)
// 8374 non-scan memory elements are identified as TIE-X. (D5)
// 8 non-scan memory elements are identified as INIT-0. (D5)
// 5 non-scan memory elements are identified as INIT-1. (D5)
// 1965 non-scan memory elements are identified as INIT-X. (D5)
// 14 non-scan memory elements are identified as TLA. (D5)
// ---------------------------------------------------------------------------
// 7856 gates may have an observable X-state. (E5)
// Warning: There were 41 BUS gates which may have possible contention. (E10) Sample_4.log
// ATPG bus checking results: pass=10, bidi=75, fail=41, abort=0, CPU time=0.00.

Example two of DRC messaging

4-6 • Tessent: Scan and ATPG: Understanding ATPG Messaging Copyright © 1999-2009 Mentor Graphics Corporation
 DRC Messaging (Cont.)
 Another ATPG DRC messaging example

// ---------------------------------------------------------------------------
// Begin RAM rules checking. Performs RAM DRC
// ---------------------------------------------------------------------------
// Warning: 194 RAMs are connected to a scan clock. (A2)
// RAM dynamic PASS_THRU testing cannot be used.
// RAM Summary Results: #RAMs = 194 #TieXs = 0 #testable = 194 #data_hold = 194
// Test Capability: #read_only = 0 #ram_sequential = 194 #seq_transparent = 0
// Write stability: #unstable_control = 0 #unstable_load = 0
// Read stability: #unstable_control = 0 #unstable_load = 0 E 5 violation reported for
// 583 gates may have an observable X-state. (E5) any gate that can create
// largest sequential test depth = 3, largest controllability depth = 2, largest observability depth = 3 an X state with its inputs
// largest test depth is on /core_inst/ram_0/U424/ (131625) (control = 0, observe = 3) at binary values
~

4-7 • Tessent: Scan and ATPG: Understanding ATPG Messaging Copyright © 1999-2009 Mentor Graphics Corporation
 ATPG Reporting
 Example of messages reported
during ATPG: Use the command
All testable faults CREate PAtterns
prior to ATPG are to start ATPG (all fault models).
put in the UC category.

By default, patterns are created

“internally” rather than read in
from an “external” file.

Deterministic patterns are

created with combinational and
sequential limits.

Performs test generation

on selected faults from
current fault list.

Dashed line is fault simulation

after ATPG to prove result.

4-8 • Tessent: Scan and ATPG: Understanding ATPG Messaging Copyright © 1999-2009 Mentor Graphics Corporation
 Special Messages in ATPG Reporting
 ATPG reports the following special messages:

// command: CREate PAtterns

// Warning: Contention on (205816), number patterns rejected = 32 . Simulated patterns with

bus contention are discarded

// Warning: Unsuccessful test for 2533 faults . Summary of aborted patterns

4-9 • Tessent: Scan and ATPG: Understanding ATPG Messaging Copyright © 1999-2009 Mentor Graphics Corporation
 Test Coverage Reporting
 ATPG reports faults as testable
or untestable.
 The following are testable (TE)
faults:
 Detected (DT):
– Det_Simulation (DS)
– Det_Implication (DI)
– Det_Robust (DR)
– Det_functional
 Posdet (PD)
– Posdet_Untestable (PU)
– Posdet_Testable (PT)
 ATPG_Untestable (AU)
 Undetected
– Uncontrolled (UC)
– Unobservable (UO)

// command: REPort STatistics

4-10 • Tessent: Scan and ATPG: Understanding ATPG Messaging Copyright © 1999-2009 Mentor Graphics Corporation
 Test Coverage Reporting (Cont.)
 The following
are untestable
Q
faults: D
X s-a-1 A B C D
QB
 Unused (UU) s-a-0
 Tied (TI)
 Blocked (BL) GND
 Redundant
(RE) Site of “Unused” Fault Sites of “Tied” Faults

VCC

X s-a-1
X

GND s-a-1
GND

Site of “Blocked” Fault Site of “Redundant” Fault

4-11 • Tessent: Scan and ATPG: Understanding ATPG Messaging Copyright © 1999-2009 Mentor Graphics Corporation
 Test Coverage Reporting (Cont.)

Test coverage: percentage of all

testable faults

Test Coverage = #DT + (#PD

* posdet_credit)
#Testable
Fault coverage: percentage Faults
of all faults
both testable and untestable

Fault Coverage = #DT + (#PD * posdet_credit)

#Total Faults

Test coverage:
recommended metric
for uncollapsed fault set

Fault
coverage

ATPG Effectiveness:
A measure of the tool’s ability to detect a
fault or prove that a test cannot be created
with current settings.
4-12 • Tessent: Scan and ATPG: Understanding ATPG Messaging Copyright © 1999-2009 Mentor Graphics Corporation
 Test Coverage Reporting: Fault Collapsing
 After Tessent FastScan or Tessent TestKompress identifies faults, faults that
behave the same are reduced, or collapsed, into one equivalent fault.
 Multiple faults are targeted with one pattern.
 Total number of generated patterns is reduced.
 EQ is the designator for equivalent faults.
(Equal to the fault listed above it in the fault list.)
 A test for one of the faults above is equal to the test for the other two.

4-13 • Tessent: Scan and ATPG: Understanding ATPG Messaging Copyright © 1999-2009 Mentor Graphics Corporation
 Test Coverage Reporting: Fault Collapsing (Cont.)
 Use the REPort FAults EQ: Equivalent to the
command to generate a list of fault listed above it in
faults added to the fault list. the fault list.
 Defaults to –All.
 List of equivalent (EQ) faults
included in –All switch.

4-14 • Tessent: Scan and ATPG: Understanding ATPG Messaging Copyright © 1999-2009 Mentor Graphics Corporation
 Determining the Cause of Undetected Faults

 REPort FAults is useful

for determining the cause of
undetected faults.
ATPG> REPort FAults -class
Fault value: ATPG_UNTESTABLE
Either 0 (for stuck-at-0) 0 AU /I$7/OUT
or 1 (for stuck-at-1)
1 EQ /I$7/IN
0 EQ /I$1/en
1 AU /I$7/OUT
0 EQ /I$7/IN
Fault code
1 EQ /I$1/en
0 AU /I$4/i1
0 AU /I$20/en
1 AU /I$20/en
Fault site 0 AU /I$2/en
1 AU /I$2/en

4-15 • Tessent: Scan and ATPG: Understanding ATPG Messaging Copyright © 1999-2009 Mentor Graphics Corporation
 Determining the Cause of Undetected Faults (Cont.)
 Untested faults are grouped
together.
 AU fault class
 Includes faults the tool is
unable to find a test pattern for.
 Testable faults become
atp_untestable due to
– Pin constraints.
– Insufficient sequential depth.
 May detect if constraints are
removed or the sequential
depth is changed.

Untested
Faults

4-16 • Tessent: Scan and ATPG: Understanding ATPG Messaging Copyright © 1999-2009 Mentor Graphics Corporation
 Determining the Cause of Undetected Faults (Cont.)

 Use the ANAlyze FAult command to identify why a fault is not

detected.

ATPG> REPort FAults

-Class ATPG_UNTESTABLE ATPG> ANAlyze FAult I$20/en -stuck_at 1
0 AU /I$7/OUT //
1 EQ /I$7/IN --------------------------------------------------------------------
0 EQ /I$1/en // Fault analysis for /I$20 (16) input en (0) stuck at 1
1 AU /I$7/OUT //
0 EQ /I$7/IN --------------------------------------------------------------------
1 EQ /I$1/en // Current fault classification = AU (atpg_untestable)
0 AU /I$4/i1 // Fault is blocked at /I$20 (16) due to tri-state enable.
0 AU /I$20/en // Controllability justification was successful (data
1 AU /I$20/en accessible using parallel_pattern 0).
0 AU /I$2/en // Pattern type: Basic_scan.
1 AU /I$2/en // Test generation cannot be performed - no unblocked
path to observe point.

Only stuck-at, path delay and transition fault types can

be analyzed using the ANAlyze FAult command.

4-17 • Tessent: Scan and ATPG: Understanding ATPG Messaging Copyright © 1999-2009 Mentor Graphics Corporation
 Lab 4: Understanding ATPG Messaging
During this lab, you will

 Read and analyze ATPG messaging.

 Learn how to determine the cause of undetected faults.
 Determine the cause of undetected faults.
 Specify areas not to target for ATPG.
 Write an external fault list.
 Use common methodologies to attain a quick estimate
of pattern coverage.

4-18 • Tessent: Scan and ATPG: Understanding ATPG Messaging Copyright © 1999-2009 Mentor Graphics Corporation